Circuit-technology co-optimization of heterogeneous hierarchical network-on-chips

Nickvash Kani, Azad Naeemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Because of the ever increasing number of cores present on a single chip, fast and energy efficient, inter-core data communication has become a major concern. Various networkon-chip (NoC) topologies and flow controls have been presented in literature. In this paper, for the first time, the benefits of a hierarchical heterogeneous NoC are quantized using a comprehensive circuit-interconnect technology co-optimization. It is demonstrated that this optimal hybrid network provides lower end-to-end latency and power consumption compared to other homogeneous solutions. It is shown that not only is there a significant decrease in latency and power, but also the hardware overhead and wiring area in such a system are significantly reduced.

Original languageEnglish (US)
Title of host publication2012 IEEE International Interconnect Technology Conference, IITC 2012
DOIs
StatePublished - Oct 1 2012
Externally publishedYes
Event2012 IEEE International Interconnect Technology Conference, IITC 2012 - San Jose, CA, United States
Duration: Jun 4 2012Jun 6 2012

Publication series

Name2012 IEEE International Interconnect Technology Conference, IITC 2012

Conference

Conference2012 IEEE International Interconnect Technology Conference, IITC 2012
CountryUnited States
CitySan Jose, CA
Period6/4/126/6/12

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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