TY - GEN
T1 - Circuit synthesis using generative adversarial networks (Gans)
AU - Guo, Tinghao
AU - Herber, Daniel R.
AU - Allison, James T.
N1 - Publisher Copyright:
� 2019 by German Aerospace Center (DLR). Published by the American Institute of Aeronautics and Astronautics, Inc.
PY - 2019
Y1 - 2019
N2 - In this article, we present a generative adversarial network (GAN) design framework for circuit synthesis design. While the existing methods, such as domain knowledge-and metaheuristic-based methods have been applied successfully in circuit synthesis, they are suited for certain types of circuits and thus limited. Recent advances in efficient circuit topology enumeration methods have proven to be useful for circuit synthesis problem with moderately-sized component catalogs; enumeration methods, however, cannot be used as a solution method for problems with large catalogs. Here we present a strategy based on Generative Adversarial Networks (GANs) that facilitates solution of synthesis problems that are too large for enumeration. A GAN is a generative unsupervised learning model where a lower-dimensional latent space is predefined as an abstract representation of the circuit topology space. The GAN is trained to learn the mapping from the latent space to circuit topology space. Circuit topologies can be produced using the generator, and a discriminator helps to improve generator quality. A comparative study is conducted using several recent GAN models, including GANs, DCGANs, WGANs, and improved WGANs. We designed and carried out a series of numerical experiments to evaluate the ability of these GANs to generate new circuit topologies and support design exploration. Two circuit synthesis case studies are presented here: frequency response matching and low-pass filter realizability. The work presented here is an effort to leverage recent advancements in artificial intelligence to 1) create the ability to solve larger synthesis problems than previously possible, and 2) gain deeper design insights into engineering synthesis problems.
AB - In this article, we present a generative adversarial network (GAN) design framework for circuit synthesis design. While the existing methods, such as domain knowledge-and metaheuristic-based methods have been applied successfully in circuit synthesis, they are suited for certain types of circuits and thus limited. Recent advances in efficient circuit topology enumeration methods have proven to be useful for circuit synthesis problem with moderately-sized component catalogs; enumeration methods, however, cannot be used as a solution method for problems with large catalogs. Here we present a strategy based on Generative Adversarial Networks (GANs) that facilitates solution of synthesis problems that are too large for enumeration. A GAN is a generative unsupervised learning model where a lower-dimensional latent space is predefined as an abstract representation of the circuit topology space. The GAN is trained to learn the mapping from the latent space to circuit topology space. Circuit topologies can be produced using the generator, and a discriminator helps to improve generator quality. A comparative study is conducted using several recent GAN models, including GANs, DCGANs, WGANs, and improved WGANs. We designed and carried out a series of numerical experiments to evaluate the ability of these GANs to generate new circuit topologies and support design exploration. Two circuit synthesis case studies are presented here: frequency response matching and low-pass filter realizability. The work presented here is an effort to leverage recent advancements in artificial intelligence to 1) create the ability to solve larger synthesis problems than previously possible, and 2) gain deeper design insights into engineering synthesis problems.
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U2 - 10.2514/6.2019-2350
DO - 10.2514/6.2019-2350
M3 - Conference contribution
AN - SCOPUS:85083943201
SN - 9781624105784
T3 - AIAA Scitech 2019 Forum
BT - AIAA Scitech 2019 Forum
PB - American Institute of Aeronautics and Astronautics Inc, AIAA
T2 - AIAA Scitech Forum, 2019
Y2 - 7 January 2019 through 11 January 2019
ER -