Circuit partitioning with complex resource constraints in FPGAs

Huiqun Liu, Kai Zhu, D. F. Wong

Research output: Contribution to conferencePaper

Abstract

In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing capacity and diverse resource types in the new FPGA architectures. We propose a network flow based method to optimally check whether a circuit or a sub-circuit is feasible for a set of available heterogeneous resources. The feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g. logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical FPGA (e.g. Actel's ES6500 FPGA family).

Original languageEnglish (US)
Pages77-84
Number of pages8
StatePublished - Jan 1 1998
Externally publishedYes
EventProceedings of the 1998 ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays, FPGA - Monterey, CA, USA
Duration: Feb 22 1998Feb 24 1998

Other

OtherProceedings of the 1998 ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays, FPGA
CityMonterey, CA, USA
Period2/22/982/24/98

ASJC Scopus subject areas

  • Computer Science(all)

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  • Cite this

    Liu, H., Zhu, K., & Wong, D. F. (1998). Circuit partitioning with complex resource constraints in FPGAs. 77-84. Paper presented at Proceedings of the 1998 ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays, FPGA, Monterey, CA, USA, .