Abstract
Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. This paper presents a network-flow based partitioning algorithm for dynamically reconfigurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.
| Original language | English (US) |
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| Pages | 187-194 |
| Number of pages | 8 |
| DOIs | |
| State | Published - 1999 |
| Externally published | Yes |
| Event | Proceedings of the 1999 ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays, FPGA-99 - Monterey, CA, USA Duration: Feb 21 1999 → Feb 23 1999 |
Conference
| Conference | Proceedings of the 1999 ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays, FPGA-99 |
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| City | Monterey, CA, USA |
| Period | 2/21/99 → 2/23/99 |
ASJC Scopus subject areas
- General Computer Science