Circuit partitioning for dynamically reconfigurable FPGAs

Huiqun Liu, D. F. Wong

Research output: Contribution to conferencePaper

Abstract

Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. This paper presents a network-flow based partitioning algorithm for dynamically reconfigurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.

Original languageEnglish (US)
Pages187-194
Number of pages8
DOIs
StatePublished - Jan 1 1999
EventProceedings of the 1999 ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays, FPGA-99 - Monterey, CA, USA
Duration: Feb 21 1999Feb 23 1999

Conference

ConferenceProceedings of the 1999 ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays, FPGA-99
CityMonterey, CA, USA
Period2/21/992/23/99

ASJC Scopus subject areas

  • Computer Science(all)

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  • Cite this

    Liu, H., & Wong, D. F. (1999). Circuit partitioning for dynamically reconfigurable FPGAs. 187-194. Paper presented at Proceedings of the 1999 ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays, FPGA-99, Monterey, CA, USA, . https://doi.org/10.1145/296399.296456