Abstract
An efficient circuit-level simulator for the prediction of time- dependent dielectric breakdown effects in digital CMOS circuits has been developed and integrated into the reliability simulation tool BERT (Berkeley Reliability Tools). The new module enhances the capability of the earlier SPICE-based oxide breakdown simulator by enabling practical simulations of large digital circuits. We discuss burn-in simulation for digital circuits and show that a significant reduction in oxide breakdown failure probability is possible.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 370-374 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Semiconductor Manufacturing |
| Volume | 8 |
| Issue number | 3 |
| DOIs | |
| State | Published - Aug 1995 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering