Abstract
This work presents circuit-level simulation and layout optimization techniques for a multifinger NMOS device. By considering the full thermal-coupling of heat sources at each drain finger, simulations reflect the device layout dependent behavior in silicon under EOS/ESD. Simulation reveals that each NMOS finger may carry a different stress current due to the non-symmetrical heat-coupling effect; as a result, the effective total NMOS width will be reduced. Simulation results agree well with the measured data. We also propose a design and layout optimization methodology which is illustrated with a design example.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 159-162 |
| Number of pages | 4 |
| Journal | Proceedings of the Custom Integrated Circuits Conference |
| State | Published - 1997 |
| Event | Proceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: May 5 1997 → May 8 1997 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering