Circuit-level simulation and layout optimization for deep submicron EOS/ESD output protection device

Tong Li, Sridhar Ramaswamy, Elyse Rosenbaum, Sung Mo Kang

Research output: Contribution to journalConference article

Abstract

This work presents circuit-level simulation and layout optimization techniques for a multifinger NMOS device. By considering the full thermal-coupling of heat sources at each drain finger, simulations reflect the device layout dependent behavior in silicon under EOS/ESD. Simulation reveals that each NMOS finger may carry a different stress current due to the non-symmetrical heat-coupling effect; as a result, the effective total NMOS width will be reduced. Simulation results agree well with the measured data. We also propose a design and layout optimization methodology which is illustrated with a design example.

Original languageEnglish (US)
Pages (from-to)159-162
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Jan 1 1997
EventProceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: May 5 1997May 8 1997

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Networks (circuits)
Silicon
Hot Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Circuit-level simulation and layout optimization for deep submicron EOS/ESD output protection device. / Li, Tong; Ramaswamy, Sridhar; Rosenbaum, Elyse; Kang, Sung Mo.

In: Proceedings of the Custom Integrated Circuits Conference, 01.01.1997, p. 159-162.

Research output: Contribution to journalConference article

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