Chip-level electrothermal simulator for temperature profile estimation of CMOS VLSI chips

Yi Kan Cheng, Chin Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung Mo Kang

Research output: Contribution to journalArticle

Abstract

In this paper, we present a chip-level electrothermal simulator, ILLIADS-T. It aims at finding the steady-state CMOS VLSI chip temperature profile and the corresponding circuit performance. With this tool, temperature-related reliability problems of VLSI chips can be accurately predicted to guide the module placement, packaging, as well as the timing verification.

Original languageEnglish (US)
Pages (from-to)580-583
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - 1996

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Simulators
Packaging
Temperature
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Chip-level electrothermal simulator for temperature profile estimation of CMOS VLSI chips. / Cheng, Yi Kan; Teng, Chin Chi; Dharchoudhury, Abhijit; Rosenbaum, Elyse; Kang, Sung Mo.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, 1996, p. 580-583.

Research output: Contribution to journalArticle

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