Charged Device Model Reliability of Three-Dimensional Integrated Circuits

The interdie signal interfaces in a three-dimensional (3-D) integrated circuit are vulnerable to overvoltage stress induced by charged device model (CDM) ESD, although they do not necessarily lie on any of the main ESD current paths. Circuit simulation shows that the magnitude of the stress is highly sensitive to the design of the ground distribution network on both the die and package levels. The placement of TSVs also impacts the stress generated at the interdie interfaces. If excessive, the voltage stress can be mitigated by placing a small ESD clamp at the interdie signal interface. A power supply domain may span multiple dies in a 3-D stack; this work investigates whether it is possible to remove the clamps from some of the dies in the stack to save silicon area without severely impacting the CDM reliability of the interdie interface circuits.