Characterizing the effects of transient faults on a high-performance processor pipeline

Nicholas J. Wang, Justin Quek, Todd M. Rafacz, Sanjay J. Patel

Research output: Contribution to conferencePaperpeer-review

Abstract

The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and protecting against single-event upsets in digital systems. In this work, the effects of transient faults on high performance microprocessors is explored. To perform a thorough exploration, a highly detailed register transfer level model of a deeply pipelined, out-of-order microprocessor was created. Using fault injection, we determined that fewer than 15% of single bit corruptions in processor state result in software visible errors. These failures were analyzed to identify the most vulnerable portions of the processor, which were then protected using simple low-overhead techniques. This resulted in a 75% reduction in failures. Building upon the failure modes seen in the microarchitecture, fault injections into software were performed to investigate the level of masking that the software layer provides. Together, the baseline microarchitectural substrate and software mask more than 9 out of 10 transient faults from affecting correct program execution.

Original languageEnglish (US)
Pages61-70
Number of pages10
DOIs
StatePublished - 2004
Event2004 International Conference on Dependable Systems and Networks - Florence, Italy
Duration: Jun 28 2004Jul 1 2004

Other

Other2004 International Conference on Dependable Systems and Networks
Country/TerritoryItaly
CityFlorence
Period6/28/047/1/04

ASJC Scopus subject areas

  • Computer Science (miscellaneous)
  • Computer Networks and Communications

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