Characterization of the performance variation for regular standard cell with process nonidealities

Hongbo Zhang, Yuelin Du, Martin D F Wong, Kai Yuan Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research work on 2-D cell characterization shows that the timing variations can be characterized by the timing model. 1,2 However, as regular design rules become necessary in sub-45nm node circuit design, 1-D design has shown its advantages and has drawn intensive research interest. The circuit performance of a 1-D standard cell can be more accurately predicted than that of a 2-D standard cell as it is insensitive to layout context. This paper presents a characterization methodology to predict the delay and power performance of 1-D standard cells. We perform lithography simulation on the poly gate array generated by dense line printing technology, which constructs the poly gates of inverters, and do statistical analysis on the data simulated within the process window. After that, circuit simulation is performed on the printed cell to obtain its delay and power performance, and the delay and power distribution curves are generated, which accurately predict the circuit performance of standard cells. In the end, the benefits of our cell characterization method are analyzed from both design and manufacturing perspectives, which shows great advantages in accurate circuit analysis and yield improving.

Original languageEnglish (US)
Title of host publicationDesign for Manufacturability through Design-Process Integration V
DOIs
StatePublished - May 16 2011
EventDesign for Manufacturability through Design-Process Integration V - San Jose, CA, United States
Duration: Mar 2 2011Mar 3 2011

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
Volume7974
ISSN (Print)0277-786X

Other

OtherDesign for Manufacturability through Design-Process Integration V
CountryUnited States
CitySan Jose, CA
Period3/2/113/3/11

Keywords

  • 1-D patterning
  • Dense line printing
  • Standard cell characterization

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

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  • Cite this

    Zhang, H., Du, Y., Wong, M. D. F., & Chao, K. Y. (2011). Characterization of the performance variation for regular standard cell with process nonidealities. In Design for Manufacturability through Design-Process Integration V [79740T] (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 7974). https://doi.org/10.1117/12.879326