Channel segmentation design for symmetrical FPGAs

Wai Kei Mak, D. F. Wong

Research output: Contribution to conferencePaperpeer-review

Abstract

The channel segmentation design problem for symmetrical FPGAs is the problem of designing segmented tracks in the interconnection channels that provides good net routability and delay performance at the same time. In this paper, we show how to separate the problem into the segmentation design problems of the vertical and horizontal channels by a statistical analysis of the net distribution on a symmetrical FPGA. And we propose an effective approach for segmented channel design when the allowed number of tracks in a channel is fixed and limited.

Original languageEnglish (US)
Pages496-501
Number of pages6
StatePublished - Dec 1 1997
Externally publishedYes
EventProceedings of the 1997 International Conference on Computer Design - Austin, TX, USA
Duration: Oct 12 1997Oct 15 1997

Other

OtherProceedings of the 1997 International Conference on Computer Design
CityAustin, TX, USA
Period10/12/9710/15/97

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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