Cell area minimization by transistor folding

T. W. Her, D. F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Tall transistors can be folded into shorter ones to reduce the layout area. In this paper, we are given two rows of transistors, one for P-type transistors and the other for N-type transistors, and our objective is to determine an optimal folding for each transistor to minimize the layout area. We present a time transistor folding algorithm to minimize the layout area relating the parameter K which is the number of implementations of each transistor due to folding, and L considered here the channel length.

Original languageEnglish (US)
Title of host publicationEuropean Design Automation Conference - Proceedings
Editors Anon
PublisherPubl by IEEE
Number of pages6
ISBN (Print)0818643528
StatePublished - 1993
Externally publishedYes

Publication series

NameEuropean Design Automation Conference - Proceedings

ASJC Scopus subject areas

  • Control and Systems Engineering


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