Cell area minimization by transistor folding

Tall transistors can be folded into shorter ones to reduce the layout area. In this paper, we are given two rows of transistors, one for P-type transistors and the other for N-type transistors, and our objective is to determine an optimal folding for each transistor to minimize the layout area. We present a time transistor folding algorithm to minimize the layout area relating the parameter K which is the number of implementations of each transistor due to folding, and L considered here the channel length.