Abstract
This work presents a CDM circuit-level model for stacked die in a BGA package. Circuit simulation is used to investigate the voltage stress on the die-to-die interface circuits. The power net connections are found to impact the CDM reliability. An ESD protection scheme for the die-to-die interface circuits is proposed.
| Original language | English (US) |
|---|---|
| Title of host publication | Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, EOS/ESD 2010 |
| State | Published - 2010 |
| Event | 32nd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2010 - Reno, NV, United States Duration: Oct 3 2010 → Oct 8 2010 |
Other
| Other | 32nd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2010 |
|---|---|
| Country/Territory | United States |
| City | Reno, NV |
| Period | 10/3/10 → 10/8/10 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering