CDM simulation study of a system-in-package

Vrashank Shukla, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This work presents a CDM circuit-level model for stacked die in a BGA package. Circuit simulation is used to investigate the voltage stress on the die-to-die interface circuits. The power net connections are found to impact the CDM reliability. An ESD protection scheme for the die-to-die interface circuits is proposed.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, EOS/ESD 2010
StatePublished - 2010
Event32nd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2010 - Reno, NV, United States
Duration: Oct 3 2010Oct 8 2010

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159


Other32nd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2010
Country/TerritoryUnited States
CityReno, NV

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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