CDM-reliable T-coil techniques for a 25-Gb/s wireline receiver front-end

An inherent CDM-electrostatic discharge (ESD) hazard exists in T-coil circuits due to magnetic coupling from the pad to the receiver input. An "inductance halving" technique is proposed to reduce magnetic coupling during ESD, thereby canceling voltage overshoot. Receiver circuits with continuoustime linear equalizers are placed on a 65-nm CMOS test chip to evaluate the performance of the proposed T-coil in comparison with the conventional T-coil with secondary ESD protection. From the eye diagram test using 25-Gb/s pseudorandom bit sequence data, the receiver with an inductance-halving T-coil shows 1.8× higher and 29% wider eye opening, as compared with the receiver with a T-coil protected by a secondary ESD device. In a very fast transmission line pulsing test, both schemes achieve around an 8-A failure current, which demonstrates that the proposed T-coil can effectively protect receiver circuits against CDM-like ESD stresses.