CCP: Common case promotion for improved timing error resilience with energy efficiency

Better-Than-Worst-case (BTW) design has been proposed as an alternative way to operate a circuit by deliberately allowing timing errors for rare cases and rectifying them with error correction mechanisms in order to achieve higher performance, better reliability guarantee, or lower energy consumption. This new design methodology necessitates the analysis and manipulation of signal probabilities during circuit optimization. This paper looks for the solution from the logic synthesis perspective and proposes a new concept, called Common Case Promotion (CCP), to enable effective circuit optimization following the BTW design methodology. CCP consists of: 1) probability-driven re-synthesis that changes a digital circuit's internal structure, 2) a dynamic behavior aware SAT-based redundancy remover that reduces area overhead, and 3) a timed characteristic function (TCF) based circuit dynamic behavior analyzer that provides optimization convergence. The experimental results show that, on average, we can effectively improve circuits' timing error resilience by 24%, which reduces the need of error recovery for BTW circuits considerably, and we can improve the overall energy efficiency by 15%.