CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses

Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau

Research output: Contribution to journalArticle

Abstract

Modern superscalar processors often suffer long stalls because of load misses in on-chip L2 caches. To address this problem, we propose hiding L2 misses with Checkpoint-Assisted VAlue prediction (CAVA). On an L2 cache miss, a predicted value is returned to the processor. When the missing load finally reaches the head of the ROB, the processor checkpoints its state, retires the load, and speculatively uses the predicted value and continues execution. When the value in memory arrives at the L2 cache, it is compared to the predicted value. If the prediction was correct, speculation has succeeded and execution continues; otherwise, execution is rolled back and restarted from the checkpoint. CAVA uses fast checkpointing, speculative buffering, and a modest-sized value prediction structure that has about 50% accuracy. Compared to an aggressive superscalar processor, CAVA speeds up execution by up to 1.45 for SPECint applications and 1.58 for SPECfp applications, with a geometric mean of 1.14 for SPECint and 1.34 for SPECfp applications. We also evaluate an implementation of Runahead execution—a previously proposed scheme that does not perform value prediction and discards all work done between checkpoint and data reception from memory. Runahead execution speeds up execution by a geometric mean of 1.07 for SPECint and 1.18 for SPECfp applications, compared to the same baseline.

Original languageEnglish (US)
Pages (from-to)182-208
Number of pages27
JournalACM Transactions on Architecture and Code Optimization
Volume3
Issue number2
DOIs
StatePublished - 2006

Keywords

  • Checkpointed processor architectures
  • Design
  • Memory hierarchies
  • Multiprocessor
  • Performance
  • Value prediction

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Hardware and Architecture

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