TY - GEN
T1 - Capillary-activated scalable microporous copper microchannels for two-phase thermal management of semiconductor materials
AU - Dewanjee, Sujan
AU - Singhal, Gaurav S.
AU - Li, Jiaqi
AU - Lohan, Danny
AU - Joshi, Shailesh N.
AU - Braun, Paul V.
AU - Miljkovic, Nenad
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Efficient thermal management of semiconductor devices is critical to enable the growth of computational power. Over the past few decades, transistor volumetric packing densities (number of transistors per unit volume) have been increasing, enabling further miniaturization of electronic chips. To address thermal constraints, the development of scalable and robust manufacturing techniques for chip-scale integrated two-phase cooling has been a topic of interest over the past decade. Copper and silicon microchannels have been studied to enable near-junction phase change heat transfer, which show a substantial increase in allowable heat flux due to enhanced evaporation, increased three phase contact line length, and more efficient pool and flow boiling. Electrodeposited metal layers as well as sintering have been used to incorporate roughness on these microchannels. Previous studies have used standard photolithography, laser etching, and deep reactive ion etching for fabricating microchannels. Due to fabrication limitations, these studies have been able to achieve channel and fin widths on the order of 5 μm to 300 μm and fin heights ranging from 10 μm to 350 μm, Here, we investigate the pool boiling performance of micro channel microporous copper structures grown scalably on silicon wafers. Unlike previous approaches, we fabricate the structure using mask-less photoresist pattern writing and electrodeposition of porous copper. Optimized design guidelines are predicted by exploring the micro channel width and microporous copper structure thickness ranging from 10 μm to 400 μm, while structure heights are kept in the range of 25 μm to 50 μm, We demonstrate an optimized pore size can be predicted in terms of durability and improved heat transfer coefficient by varying current density from 20 mA/cm2 to 1 A/cm2 during fabrication. We analyze bubble dynamics during water pool boiling on the fabricated structures to find out the reason behind the results found. The results show prominent increases in critical heat flux and heat transfer coefficient due to escalated capillary activation stemming from the porous interconnected structures. Our work not only explores a distinctive, durable and scalable fabrication method for cooling devices on semiconductors, but also develops guidelines for the scalable and facile development of high-capillarity conductive porous structures.
AB - Efficient thermal management of semiconductor devices is critical to enable the growth of computational power. Over the past few decades, transistor volumetric packing densities (number of transistors per unit volume) have been increasing, enabling further miniaturization of electronic chips. To address thermal constraints, the development of scalable and robust manufacturing techniques for chip-scale integrated two-phase cooling has been a topic of interest over the past decade. Copper and silicon microchannels have been studied to enable near-junction phase change heat transfer, which show a substantial increase in allowable heat flux due to enhanced evaporation, increased three phase contact line length, and more efficient pool and flow boiling. Electrodeposited metal layers as well as sintering have been used to incorporate roughness on these microchannels. Previous studies have used standard photolithography, laser etching, and deep reactive ion etching for fabricating microchannels. Due to fabrication limitations, these studies have been able to achieve channel and fin widths on the order of 5 μm to 300 μm and fin heights ranging from 10 μm to 350 μm, Here, we investigate the pool boiling performance of micro channel microporous copper structures grown scalably on silicon wafers. Unlike previous approaches, we fabricate the structure using mask-less photoresist pattern writing and electrodeposition of porous copper. Optimized design guidelines are predicted by exploring the micro channel width and microporous copper structure thickness ranging from 10 μm to 400 μm, while structure heights are kept in the range of 25 μm to 50 μm, We demonstrate an optimized pore size can be predicted in terms of durability and improved heat transfer coefficient by varying current density from 20 mA/cm2 to 1 A/cm2 during fabrication. We analyze bubble dynamics during water pool boiling on the fabricated structures to find out the reason behind the results found. The results show prominent increases in critical heat flux and heat transfer coefficient due to escalated capillary activation stemming from the porous interconnected structures. Our work not only explores a distinctive, durable and scalable fabrication method for cooling devices on semiconductors, but also develops guidelines for the scalable and facile development of high-capillarity conductive porous structures.
KW - Microchannels
KW - capillary activated
KW - thermal management
KW - wettability
KW - wickability
UR - http://www.scopus.com/inward/record.url?scp=85166188464&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85166188464&partnerID=8YFLogxK
U2 - 10.1109/ITherm55368.2023.10177496
DO - 10.1109/ITherm55368.2023.10177496
M3 - Conference contribution
AN - SCOPUS:85166188464
T3 - InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITHERM
BT - Proceedings of the 22nd InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2023
PB - IEEE Computer Society
T2 - 22nd InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2023
Y2 - 30 May 2023 through 2 June 2023
ER -