Calculation of the phonon-limited mobility in silicon Gate All-Around MOSFETs

A. Godoy; F. Ruiz; C. Sampedro; F. Gámiz; U. Ravaioli

doi:10.1016/j.sse.2007.07.025

Calculation of the phonon-limited mobility in silicon Gate All-Around MOSFETs

A. Godoy, F. Ruiz, C. Sampedro, F. Gámiz, U. Ravaioli

Research output: Contribution to journal › Article › peer-review

Abstract

The continuous reduction of device dimensions and the design of new silicon-on-insulator (SOI) structures which confine the carriers in two dimensions (2D) have a considerable influence on electron transport properties. The aim of this work is to study the phonon-limited electron mobility in silicon nanowires where the carriers are confined in 2D and we are dealing with a 1D electron gas. It has been found that for devices with silicon cross-sections below 10 nm, the overlap factor rapidly increases, producing a notable degradation of the phonon-limited mobility.

Original language	English (US)
Pages (from-to)	1211-1215
Number of pages	5
Journal	Solid-State Electronics
Volume	51
Issue number	9
DOIs	https://doi.org/10.1016/j.sse.2007.07.025
State	Published - Sep 2007

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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title = "Calculation of the phonon-limited mobility in silicon Gate All-Around MOSFETs",

abstract = "The continuous reduction of device dimensions and the design of new silicon-on-insulator (SOI) structures which confine the carriers in two dimensions (2D) have a considerable influence on electron transport properties. The aim of this work is to study the phonon-limited electron mobility in silicon nanowires where the carriers are confined in 2D and we are dealing with a 1D electron gas. It has been found that for devices with silicon cross-sections below 10 nm, the overlap factor rapidly increases, producing a notable degradation of the phonon-limited mobility.",

author = "A. Godoy and F. Ruiz and C. Sampedro and F. G{\'a}miz and U. Ravaioli",

note = "Funding Information: This work was supported in part by the Spanish Government through Research Projects FIS2005-06832 and Grant No. PR-2006-0233 and Junta de Andaluc{\'i}a within the framework of Research Project TIC-00831. U.R. acknowledges support from the Network for Computational Nanotechnology NSF Grant EEC-0228390. ",

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AU - Godoy, A.

AU - Ruiz, F.

AU - Sampedro, C.

AU - Gámiz, F.

AU - Ravaioli, U.

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AB - The continuous reduction of device dimensions and the design of new silicon-on-insulator (SOI) structures which confine the carriers in two dimensions (2D) have a considerable influence on electron transport properties. The aim of this work is to study the phonon-limited electron mobility in silicon nanowires where the carriers are confined in 2D and we are dealing with a 1D electron gas. It has been found that for devices with silicon cross-sections below 10 nm, the overlap factor rapidly increases, producing a notable degradation of the phonon-limited mobility.

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