BulkSMT: Designing SMT processors for atomic-block execution

Xuehai Qian, Benjamin Sahelices, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multiprocessor architectures that continuously execute atomic blocks (or chunks) of instructions can improve performance and software productivity. However, all of the prior proposals for such architectures assume single-context cores as building blocks - rather than the widely-used Simultaneous Multithreading (SMT) cores. As a result, they are underutilizing hardware resources. This paper presents the first SMT design that supports continuous chunked (or transactional) execution of its contexts. Our design, called BulkSMT, can be used either in a single-core processor or in a multicore of SMTs. We present a set of BulkSMT configurations with different cost and performance. We also describe the architectural primitives that enable chunked execution in an SMT core and in a multicore of SMTs. Our results, based on simulations of SPLASH-2 and PARSEC codes, show that BulkSMT supports chunked execution cost-effectively. In a 4-core multicore with eager chunked execution, BulkSMT reduces the execution time of the applications by an average of 26% compared to running on single-context cores. In a single core, the average reduction is 32%.

Original languageEnglish (US)
Title of host publicationProceedings - 18th IEEE International Symposium on High Performance Computer Architecture, HPCA - 18 2012
Pages153-164
Number of pages12
DOIs
StatePublished - May 3 2012
Event18th IEEE International Symposium on High Performance Computer Architecture, HPCA - 18 2012 - New Orleans, LA, United States
Duration: Feb 25 2012Feb 29 2012

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other18th IEEE International Symposium on High Performance Computer Architecture, HPCA - 18 2012
CountryUnited States
CityNew Orleans, LA
Period2/25/122/29/12

ASJC Scopus subject areas

  • Hardware and Architecture

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    Qian, X., Sahelices, B., & Torrellas, J. (2012). BulkSMT: Designing SMT processors for atomic-block execution. In Proceedings - 18th IEEE International Symposium on High Performance Computer Architecture, HPCA - 18 2012 (pp. 153-164). [6168952] (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2012.6168952