Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions

J. Wu, P. Juliano, E. Rosenbaum

Research output: Contribution to journalArticle

Abstract

Time-dependent dielectric breakdown of 2.2-4.7 nm gate oxides is investigated down to the nanosecond time regime. The so-called 1/E model best fits the time-to-breakdown data. Latent damage is also examined and it is seen that the trap generation rate, i.e., the damage rate, is pulse-width dependent, and, thus, d.c. data should not be used to predict the degradation rate under ESD-type stress conditions. Voltage overshoots and a slow turn-on time make low voltage triggered silicon controlled rectifiers bad candidates for protecting the ultra-thin gate oxide against CDM stress.

Original languageEnglish (US)
Pages (from-to)1771-1779
Number of pages9
JournalMicroelectronics Reliability
Volume41
Issue number11
DOIs
StatePublished - Nov 1 2001

Fingerprint

Oxides
breakdown
damage
oxides
Electric potential
Electric breakdown
Thyristors
silicon controlled rectifiers
Degradation
low voltage
pulse duration
traps
degradation
electric potential

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Safety, Risk, Reliability and Quality
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Cite this

Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions. / Wu, J.; Juliano, P.; Rosenbaum, E.

In: Microelectronics Reliability, Vol. 41, No. 11, 01.11.2001, p. 1771-1779.

Research output: Contribution to journalArticle

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