Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions

J. Wu, P. Juliano, E. Rosenbaum

Research output: Contribution to journalArticlepeer-review


Time-dependent dielectric breakdown of 2.2-4.7 nm gate oxides is investigated down to the nanosecond time regime. The so-called 1/E model best fits the time-to-breakdown data. Latent damage is also examined and it is seen that the trap generation rate, i.e., the damage rate, is pulse-width dependent, and, thus, d.c. data should not be used to predict the degradation rate under ESD-type stress conditions. Voltage overshoots and a slow turn-on time make low voltage triggered silicon controlled rectifiers bad candidates for protecting the ultra-thin gate oxide against CDM stress.

Original languageEnglish (US)
Pages (from-to)1771-1779
Number of pages9
JournalMicroelectronics Reliability
Issue number11
StatePublished - Nov 2001

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Safety, Risk, Reliability and Quality
  • Surfaces, Coatings and Films
  • Atomic and Molecular Physics, and Optics
  • Electrical and Electronic Engineering


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