Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions

Time-dependent dielectric breakdown of 2.2-4.7 nm gate oxides is investigated down to the nanosecond time regime. The so-called 1/E model best fits the time-to-breakdown data. Latent damage is also examined and it is seen that the trap generation rate, i.e., the damage rate, is pulse-width dependent, and, thus, d.c. data should not be used to predict the degradation rate under ESD-type stress conditions. Voltage overshoots and a slow turn-on time make low voltage triggered silicon controlled rectifiers bad candidates for protecting the ultra-thin gate oxide against CDM stress.