Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions

J. Wu, P. Juliano, E. Rosenbaum

Research output: Contribution to journalConference articlepeer-review


Time-dependent dielectric breakdown of 2.2-4.7 nm gate oxides is investigated down to the nanosecond time regime. The so-called l/E model best fits the time-to-breakdown data. Latent damage is also examined and it is seen that the trap generation rate, i.e., the damage rate, is pulse-width dependent; and, thus, dc data should not be used to predict the degradation rate under ESD-type stress conditions. Voltage overshoots and a slow turn-on time make LVTSCRs bad candidates for protecting the ultra-thin gate oxide against CDM stress.

Original languageEnglish (US)
Pages (from-to)287-295
Number of pages9
JournalElectrical Overstress/Electrostatic Discharge Symposium Proceedings
StatePublished - 2000
EventElectrical Overstress/Electrostatic Discharge Symposium Proceedings - Anaheim, CA, USA
Duration: Sep 26 2000Sep 28 2000

ASJC Scopus subject areas

  • Condensed Matter Physics


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