TY - JOUR
T1 - Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions
AU - Wu, J.
AU - Juliano, P.
AU - Rosenbaum, E.
N1 - Funding Information:
This work was supported by research grants from the Semiconductor Research Corporation and National Science Foundation.
PY - 2000
Y1 - 2000
N2 - Time-dependent dielectric breakdown of 2.2-4.7 nm gate oxides is investigated down to the nanosecond time regime. The so-called l/E model best fits the time-to-breakdown data. Latent damage is also examined and it is seen that the trap generation rate, i.e., the damage rate, is pulse-width dependent; and, thus, dc data should not be used to predict the degradation rate under ESD-type stress conditions. Voltage overshoots and a slow turn-on time make LVTSCRs bad candidates for protecting the ultra-thin gate oxide against CDM stress.
AB - Time-dependent dielectric breakdown of 2.2-4.7 nm gate oxides is investigated down to the nanosecond time regime. The so-called l/E model best fits the time-to-breakdown data. Latent damage is also examined and it is seen that the trap generation rate, i.e., the damage rate, is pulse-width dependent; and, thus, dc data should not be used to predict the degradation rate under ESD-type stress conditions. Voltage overshoots and a slow turn-on time make LVTSCRs bad candidates for protecting the ultra-thin gate oxide against CDM stress.
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M3 - Conference article
AN - SCOPUS:0034538958
SN - 0739-5159
SP - 287
EP - 295
JO - Electrical Overstress/Electrostatic Discharge Symposium Proceedings
JF - Electrical Overstress/Electrostatic Discharge Symposium Proceedings
T2 - Electrical Overstress/Electrostatic Discharge Symposium Proceedings
Y2 - 26 September 2000 through 28 September 2000
ER -