Branch recovery with compiler-assisted multiple instruction retry

N. J. Alewine, S. K. Chen, C. C. Li, W. K. Fuchs, W. M. Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A compiler-assisted approach to implementing multiple instruction retry has recently been developed by C.-C. J Li et al. (1991). They extend compiler-assisted multiple instruction retry to include a broad class of code execution failures. Five benchmarks were used to measure the performance penalty of hazard resolution. Results indicate that the enhanced pure software approach can produce performance penalties consistent with existing hardware techniques. A combined compiler/hardware resolution strategy is also described and was evaluated. Experimental results indicate a lower performance penalty than with either a totally hardware or totally software approach.

Original languageEnglish (US)
Title of host publicationFTCS 1992 - 22nd Annual International Symposium on Fault-Tolerant Computing
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages66-73
Number of pages8
ISBN (Electronic)0818628758, 9780818628757
DOIs
StatePublished - Jan 1 1992
Event22nd Annual International Symposium on Fault-Tolerant Computing, FTCS 1992 - Boston, United States
Duration: Jul 8 1992Jul 10 1992

Publication series

NameFTCS 1992 - 22nd Annual International Symposium on Fault-Tolerant Computing

Conference

Conference22nd Annual International Symposium on Fault-Tolerant Computing, FTCS 1992
CountryUnited States
CityBoston
Period7/8/927/10/92

ASJC Scopus subject areas

  • Software
  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture

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