Boosting the Accuracy of SRAM-Based in-Memory Architectures Via Maximum Likelihood-Based Error Compensation Method

Hyungyo Kim, Naresh Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

SRAM-based analog in-memory computing (IMC) architectures have demonstrated high energy efficiency and compute density over digital accelerators for machine learning. However, their compute SNR and achievable dot product (DP) dimension are limited by the analog nature of computations. We present a Maximum Likelihood (ML)-based statistical Error Compensation (MLEC) method to enhance the accuracy of binary DPs in a 6T SRAM-based IMC. MLEC leverages the IMC architecture to extract multiple observations and implements an approximate ML detection rule. Employing simulations in a 28nm CMOS and behavioral modeling, we show that MLEC enhances the compute SNR by 5dB-to-30dB over a conventional IMC with an energy overhead ranging from 10%-to-30% for DP dimensions of 64-to-256.

Original languageEnglish (US)
Title of host publicationICASSP 2023 - 2023 IEEE International Conference on Acoustics, Speech and Signal Processing, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728163277
DOIs
StatePublished - 2023
Externally publishedYes
Event48th IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2023 - Rhodes Island, Greece
Duration: Jun 4 2023Jun 10 2023

Publication series

NameICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume2023-June
ISSN (Print)1520-6149

Conference

Conference48th IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2023
Country/TerritoryGreece
CityRhodes Island
Period6/4/236/10/23

Keywords

  • in-memory computing
  • maximum likelihood detection
  • statistical error compensation

ASJC Scopus subject areas

  • Software
  • Signal Processing
  • Electrical and Electronic Engineering

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