Bolt: Faster reconfiguration in operating systems

Sankaralingam Panneerselvam, Michael M. Swift, Nam Sung Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Dynamic resource scaling enables provisioning extra resources during peak loads and saving energy by reclaiming those resources during off-peak times. Scaling the number of CPU cores is particularly valuable as it allows power savings during low-usage periods. Current systems perform scaling with a slow hotplug mechanism, which was primarily designed to remove or replace faulty cores. The high cost of scaling is reflected in power management policies that perform scaling at coarser time scales to amortize the high reconfiguration latency. We describe Bolt, a new mechanism built on existing hotplug infrastructure to reduce scaling latency. Bolt also supports a new bulk interface to add or remove multiple cores at once. We implemented Bolt for x86 and ARM architectures. Our evaluation shows that Bolt can achieve over 20x speedup for entering offline state. While turning on CPUs, Bolt achieve speedups of 1.3x and 21x for x86 and ARM. The speedup is limited by high latency hardware intialization. On an ideal processor with zerolatency initialization, the speedup on x86 rises to 10x.

Original languageEnglish (US)
Title of host publicationProceedings of the 2015 USENIX Annual Technical Conference, USENIX ATC 2015
PublisherUSENIX Association
Pages511-516
Number of pages6
ISBN (Electronic)9781931971225
StatePublished - 2015
Externally publishedYes
Event2015 USENIX Annual Technical Conference, USENIX ATC 2015 - Santa Clara, United States
Duration: Jul 8 2015Jul 10 2015

Publication series

NameProceedings of the 2015 USENIX Annual Technical Conference, USENIX ATC 2015

Conference

Conference2015 USENIX Annual Technical Conference, USENIX ATC 2015
CountryUnited States
CitySanta Clara
Period7/8/157/10/15

ASJC Scopus subject areas

  • Computer Science(all)

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