BLTESTI: Benchmarking Lightweight TinyJAMBU on Embedded Systems for Trusted IoT

Mohamed El-Hadedy, Russell Hua, Shahzman Saqib, Kazutomo Yoshii, Wen Mei Hwu, Martin Margala

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Embedded systems face an increasing number of attacks, necessitating improved security measures. However, the physical constraints of these devices often limit the use of traditional cryptographic techniques. To address this challenge, NIST organized a competition focused on lightweight cryptographic algorithms (LWC) tailored for embedded systems, aiming to minimize resource usage in low-power devices. This paper benchmarks the Rust, C, and Golang programming languages, considering their advantages in memory safety, portability, and concurrency, to implement the LWC algorithm finalist named TinyJAMBU. TinyJAMBU utilizes the non-linear feedback shift register (NLFSR) model as a core security element. The evaluation is conducted on embedded systems and FPGAs to determine the optimal strategy for mapping LWC cryptographic algorithms onto resource-constrained devices. Among the three languages, the C-based implementation achieves the highest runtime efficiency, while TinyGo demonstrates the lowest power consumption. Rust falls between the two, indicating trade-offs associated with each language. Despite its larger memory footprint of 73kB, the C-based implementation of TinyJAMBU outperforms other language implementations, achieving a faster runtime of ≈ 81 seconds for the same algorithm and 4-byte message size. Golang exhibits the smallest memory footprint of 19kB, while Rust's memory footprint falls between the other two at 66kB. Furthermore, implementing TinyJAMBU on an FPGA using software-hardware partitioning with MicroBlaze takes ≈ 6.30 seconds to complete 10,000 encryption and decryption cycles, consuming around 1.09W of power. Although employing a proposed NLFSR co-processor with MicroBlaze for the 128-bit version of TinyJAMBU may not be the fastest approach, the reconfigurable nature of FPGAs allows for replicating the co-processor multiple times, offering significant advantages over the current state-of-the-art architecture of embedded systems.

Original languageEnglish (US)
Title of host publicationProceedings - 2023 IEEE 36th International System-on-Chip Conference, SOCC 2023
EditorsJurgen Becker, Andrew Marshall, Tanja Harbaum, Amlan Ganguly, Fahad Siddiqui, Kieran McLaughlin
PublisherIEEE Computer Society
ISBN (Electronic)9798350300116
StatePublished - 2023
Externally publishedYes
Event36th IEEE International System-on-Chip Conference, SOCC 2023 - Santa Clara, United States
Duration: Sep 5 2023Sep 8 2023

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706


Conference36th IEEE International System-on-Chip Conference, SOCC 2023
Country/TerritoryUnited States
CitySanta Clara


  • C
  • FPGA
  • IoT
  • Lightweight Cryptography
  • Low-Power Embedded Systems
  • MicroBlaze
  • Rust
  • TinyGo

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering


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