Better by a HAIR: Hardware-amenable Internet routing

Brent Mochizuki, Firat Kiyak, Eric Keller, Matthew Caesar

Research output: Contribution to journalArticlepeer-review


Higher-level Internet protocols are typically designed to be implemented in software. As scaling challenges increase, however, conventional software-based protocol processor architectures start to hit performance walls. Recent advances in programmable hardware and high-level hardware description languages provide the opportunity to implement some of these protocols directly in hardware. Such implementations allow designs to take advantage of the parallelization and customizability of the underlying hardware to improve performance, however, these potential performance gains are reliant on being able to efficiently and effectively process the protocol in hardware. In this paper, we suggest that hardware-based implementations should be considered while designing such protocols. To demonstrate the benefits in this, we study Internet routing, using BGP as a case study. We propose an architecture and logical design for processing BGP in hardware and enumerate sources of complexity and performance bottlenecks. We then compare this to our modified version of BGP which retains the features of BGP but is designed with a hardware implementation in mind. We show that a few changes to the protocol improve processing time and throughput by an order of magnitude.

Original languageEnglish (US)
Pages (from-to)999-1010
Number of pages12
JournalComputer Networks
Issue number4
StatePublished - Mar 10 2011
Externally publishedYes


  • BGP
  • FPGA
  • Hardware
  • Internet routing
  • Protocols

ASJC Scopus subject areas

  • Computer Networks and Communications


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