Berkeley Reliability Tools (BERT) simulates the circuit degradation (drift) due to hot-electron degradation in MOSFET's and bipolar transistors and predicts circuit failure rates due to oxide breakdown and electromigration in CMOS, bipolar, and BiCMOS circuits. With the increasing importance of reliability in today's and future technology, a reliability simulator such as this is expected to serve as the engine of “design-for-reliability” in a “building-in-reliability” paradigm. BERT works in conjunction with a circuit simulator such as SPICE in order to simulate reliability for actual circuits, and like SPICE, acts as an interactive tool for design. In this paper, we introduce BERT and summarize the current work being done. Furthermore, we will use BERT to study the reliability of a BiCMOS inverter chain and present performance data.
|Original language||English (US)|
|Number of pages||11|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Oct 1993|
ASJC Scopus subject areas
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering