BER-based adaptive ADC-equalizer based receiver for communication links

Rajan Narasimha, Naresh Shanbhag, Andrew Singer

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper presents the architecture of a non-uniform reference level bit error-rate (BER)-optimal analog-to-digital converter (ADC) and equalizer, for high-speed communication links. Finite precision analysis demonstrates that the use of the BER-optimal ADC does not increase the equalizer complexity/power significantly. An adaptive algorithm referred to as the approximate minimum BER algorithm (AMBER) is proposed in order to determine the BER-optimal reference levels. Finite-precision analysis of AMBER indicates that reference levels represented with 9-bit precision is sufficient for a 3-bit BER-optimal ADC to achieve BER equal to that of a 4-bit conventional ADC. An architectural implementation of AMBER is also presented. The reference-level adaptation unit (RL-UD) has a full-adder (FA) complexity that is 76% over the conventional adaptive equalizer. The RL-UD block is clock-gated after convergence and hence does not present a power overhead. Thus, for high-speed links employing the flash ADC architecture, the proposed AMBER receiver represents a power savings of approximately 50% in the ADC.

Original languageEnglish (US)
Title of host publication2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - Proceedings
Number of pages6
StatePublished - 2010
Event2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - San Francisco, CA, United States
Duration: Oct 6 2010Oct 8 2010

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130


Other2010 IEEE Workshop on Signal Processing Systems, SiPS 2010
Country/TerritoryUnited States
CitySan Francisco, CA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture


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