TY - GEN
T1 - BER-based adaptive ADC-equalizer based receiver for communication links
AU - Narasimha, Rajan
AU - Shanbhag, Naresh
AU - Singer, Andrew
PY - 2010
Y1 - 2010
N2 - This paper presents the architecture of a non-uniform reference level bit error-rate (BER)-optimal analog-to-digital converter (ADC) and equalizer, for high-speed communication links. Finite precision analysis demonstrates that the use of the BER-optimal ADC does not increase the equalizer complexity/power significantly. An adaptive algorithm referred to as the approximate minimum BER algorithm (AMBER) is proposed in order to determine the BER-optimal reference levels. Finite-precision analysis of AMBER indicates that reference levels represented with 9-bit precision is sufficient for a 3-bit BER-optimal ADC to achieve BER equal to that of a 4-bit conventional ADC. An architectural implementation of AMBER is also presented. The reference-level adaptation unit (RL-UD) has a full-adder (FA) complexity that is 76% over the conventional adaptive equalizer. The RL-UD block is clock-gated after convergence and hence does not present a power overhead. Thus, for high-speed links employing the flash ADC architecture, the proposed AMBER receiver represents a power savings of approximately 50% in the ADC.
AB - This paper presents the architecture of a non-uniform reference level bit error-rate (BER)-optimal analog-to-digital converter (ADC) and equalizer, for high-speed communication links. Finite precision analysis demonstrates that the use of the BER-optimal ADC does not increase the equalizer complexity/power significantly. An adaptive algorithm referred to as the approximate minimum BER algorithm (AMBER) is proposed in order to determine the BER-optimal reference levels. Finite-precision analysis of AMBER indicates that reference levels represented with 9-bit precision is sufficient for a 3-bit BER-optimal ADC to achieve BER equal to that of a 4-bit conventional ADC. An architectural implementation of AMBER is also presented. The reference-level adaptation unit (RL-UD) has a full-adder (FA) complexity that is 76% over the conventional adaptive equalizer. The RL-UD block is clock-gated after convergence and hence does not present a power overhead. Thus, for high-speed links employing the flash ADC architecture, the proposed AMBER receiver represents a power savings of approximately 50% in the ADC.
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U2 - 10.1109/SIPS.2010.5624766
DO - 10.1109/SIPS.2010.5624766
M3 - Conference contribution
AN - SCOPUS:78650387399
SN - 9781424489336
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SP - 64
EP - 69
BT - 2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - Proceedings
T2 - 2010 IEEE Workshop on Signal Processing Systems, SiPS 2010
Y2 - 6 October 2010 through 8 October 2010
ER -