TY - GEN
T1 - Behavioral-level IP integration in high-level synthesis
AU - Yang, Liwei
AU - Gurumani, Swathi
AU - Chen, Deming
AU - Rupnow, Kyle
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/1/25
Y1 - 2016/1/25
N2 - High level synthesis (HLS) quality improvements have led to its increased adoption in hardware design. In the design flow, IP reuse is critical for achieving quality of results, yet current HLS tools allow only a small set of tool-provided IPs integrated during HLS. General IP integration is then handled as an additional step either manually or using other system level tools. Performing post-HLS integration of IPs requires a clear separation of IPs from HLS-generated cores, requiring significant partitioning effort. In contrast, behavioral-level IP integration during HLS can simplify the design flow while still supporting HLS-based optimization and design space exploration. In this paper, we develop a general IP integration framework for HLS that supports fixed-and variable-latency IPs without requiring application partitioning. Using this framework that allows user-specified function/instruction-To-IP mapping, we demonstrate integration of both synthesizable and non-synthesizable IPs.
AB - High level synthesis (HLS) quality improvements have led to its increased adoption in hardware design. In the design flow, IP reuse is critical for achieving quality of results, yet current HLS tools allow only a small set of tool-provided IPs integrated during HLS. General IP integration is then handled as an additional step either manually or using other system level tools. Performing post-HLS integration of IPs requires a clear separation of IPs from HLS-generated cores, requiring significant partitioning effort. In contrast, behavioral-level IP integration during HLS can simplify the design flow while still supporting HLS-based optimization and design space exploration. In this paper, we develop a general IP integration framework for HLS that supports fixed-and variable-latency IPs without requiring application partitioning. Using this framework that allows user-specified function/instruction-To-IP mapping, we demonstrate integration of both synthesizable and non-synthesizable IPs.
KW - Behavioral-Level Integration
KW - High-Level Synthesis
KW - IP Integration
UR - http://www.scopus.com/inward/record.url?scp=84963582754&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84963582754&partnerID=8YFLogxK
U2 - 10.1109/FPT.2015.7393144
DO - 10.1109/FPT.2015.7393144
M3 - Conference contribution
AN - SCOPUS:84963582754
T3 - 2015 International Conference on Field Programmable Technology, FPT 2015
SP - 172
EP - 175
BT - 2015 International Conference on Field Programmable Technology, FPT 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - International Conference on Field Programmable Technology, FPT 2015
Y2 - 7 December 2015 through 9 December 2015
ER -