Behavioral-level IP integration in high-level synthesis

Liwei Yang, Swathi Gurumani, Deming Chen, Kyle Rupnow

Research output: Chapter in Book/Report/Conference proceedingConference contribution


High level synthesis (HLS) quality improvements have led to its increased adoption in hardware design. In the design flow, IP reuse is critical for achieving quality of results, yet current HLS tools allow only a small set of tool-provided IPs integrated during HLS. General IP integration is then handled as an additional step either manually or using other system level tools. Performing post-HLS integration of IPs requires a clear separation of IPs from HLS-generated cores, requiring significant partitioning effort. In contrast, behavioral-level IP integration during HLS can simplify the design flow while still supporting HLS-based optimization and design space exploration. In this paper, we develop a general IP integration framework for HLS that supports fixed-and variable-latency IPs without requiring application partitioning. Using this framework that allows user-specified function/instruction-To-IP mapping, we demonstrate integration of both synthesizable and non-synthesizable IPs.

Original languageEnglish (US)
Title of host publication2015 International Conference on Field Programmable Technology, FPT 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)9781467390910
StatePublished - Jan 25 2016
EventInternational Conference on Field Programmable Technology, FPT 2015 - Queenstown, New Zealand
Duration: Dec 7 2015Dec 9 2015

Publication series

Name2015 International Conference on Field Programmable Technology, FPT 2015


OtherInternational Conference on Field Programmable Technology, FPT 2015
Country/TerritoryNew Zealand


  • Behavioral-Level Integration
  • High-Level Synthesis
  • IP Integration

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Software


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