BDD-based circuit restructuring for reducing dynamic power

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As advances in process technology continue to scale down transistors, low power design is becoming more critical. Clock gating is a dynamic power saving technique that can freeze some flip-flops and prevent portion of the circuit from unneeded switching. In this paper, we consider fine-grained clock gating through pipelining, in which control signals from one pipeline stage are used to freeze some logic in the next pipeline stage. We present a novel BDD-based decomposition algorithm to restructure the circuit and expose possible control signals that would maximize power saving. We then use ILP formulation to select the optimal set of control signals for the circuit. We show that the constraint matrix is totally unimodular, and solve this selection problem optimally using linear programming. Comparing to a previous work [7], we get similar and 9% better dynamic power saving for small and medium circuits, respectively. For the largest MCNC circuits, which the previous technique cannot handle, we get an average of 19% dynamic power saving with 9.3% area overhead comparing to the original, non-restructured circuits.

Original languageEnglish (US)
Title of host publication2010 IEEE International Conference on Computer Design, ICCD 2010
Pages548-554
Number of pages7
DOIs
StatePublished - Dec 1 2010
Event28th IEEE International Conference on Computer Design, ICCD 2010 - Amsterdam, Netherlands
Duration: Oct 3 2010Oct 6 2010

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)1063-6404

Other

Other28th IEEE International Conference on Computer Design, ICCD 2010
CountryNetherlands
CityAmsterdam
Period10/3/1010/6/10

Fingerprint

Networks (circuits)
Clocks
Pipelines
Inductive logic programming (ILP)
Flip flop circuits
Linear programming
Transistors
Decomposition

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Dinh, Q., Chen, D., & Wong, M. D. F. (2010). BDD-based circuit restructuring for reducing dynamic power. In 2010 IEEE International Conference on Computer Design, ICCD 2010 (pp. 548-554). [5647524] (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). https://doi.org/10.1109/ICCD.2010.5647524

BDD-based circuit restructuring for reducing dynamic power. / Dinh, Quang; Chen, Deming; Wong, Martin D F.

2010 IEEE International Conference on Computer Design, ICCD 2010. 2010. p. 548-554 5647524 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dinh, Q, Chen, D & Wong, MDF 2010, BDD-based circuit restructuring for reducing dynamic power. in 2010 IEEE International Conference on Computer Design, ICCD 2010., 5647524, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 548-554, 28th IEEE International Conference on Computer Design, ICCD 2010, Amsterdam, Netherlands, 10/3/10. https://doi.org/10.1109/ICCD.2010.5647524
Dinh Q, Chen D, Wong MDF. BDD-based circuit restructuring for reducing dynamic power. In 2010 IEEE International Conference on Computer Design, ICCD 2010. 2010. p. 548-554. 5647524. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). https://doi.org/10.1109/ICCD.2010.5647524
Dinh, Quang ; Chen, Deming ; Wong, Martin D F. / BDD-based circuit restructuring for reducing dynamic power. 2010 IEEE International Conference on Computer Design, ICCD 2010. 2010. pp. 548-554 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).
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