TY - GEN
T1 - BDD-based circuit restructuring for reducing dynamic power
AU - Dinh, Quang
AU - Chen, Deming
AU - Wong, Martin D.F.
PY - 2010
Y1 - 2010
N2 - As advances in process technology continue to scale down transistors, low power design is becoming more critical. Clock gating is a dynamic power saving technique that can freeze some flip-flops and prevent portion of the circuit from unneeded switching. In this paper, we consider fine-grained clock gating through pipelining, in which control signals from one pipeline stage are used to freeze some logic in the next pipeline stage. We present a novel BDD-based decomposition algorithm to restructure the circuit and expose possible control signals that would maximize power saving. We then use ILP formulation to select the optimal set of control signals for the circuit. We show that the constraint matrix is totally unimodular, and solve this selection problem optimally using linear programming. Comparing to a previous work [7], we get similar and 9% better dynamic power saving for small and medium circuits, respectively. For the largest MCNC circuits, which the previous technique cannot handle, we get an average of 19% dynamic power saving with 9.3% area overhead comparing to the original, non-restructured circuits.
AB - As advances in process technology continue to scale down transistors, low power design is becoming more critical. Clock gating is a dynamic power saving technique that can freeze some flip-flops and prevent portion of the circuit from unneeded switching. In this paper, we consider fine-grained clock gating through pipelining, in which control signals from one pipeline stage are used to freeze some logic in the next pipeline stage. We present a novel BDD-based decomposition algorithm to restructure the circuit and expose possible control signals that would maximize power saving. We then use ILP formulation to select the optimal set of control signals for the circuit. We show that the constraint matrix is totally unimodular, and solve this selection problem optimally using linear programming. Comparing to a previous work [7], we get similar and 9% better dynamic power saving for small and medium circuits, respectively. For the largest MCNC circuits, which the previous technique cannot handle, we get an average of 19% dynamic power saving with 9.3% area overhead comparing to the original, non-restructured circuits.
UR - http://www.scopus.com/inward/record.url?scp=78650742008&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78650742008&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2010.5647524
DO - 10.1109/ICCD.2010.5647524
M3 - Conference contribution
AN - SCOPUS:78650742008
SN - 9781424489350
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 548
EP - 554
BT - 2010 IEEE International Conference on Computer Design, ICCD 2010
T2 - 28th IEEE International Conference on Computer Design, ICCD 2010
Y2 - 3 October 2010 through 6 October 2010
ER -