@inproceedings{ee537dbcfe3442a0a03637fae04e7980,
title = "BayesPerf: Minimizing performance monitoring errors using Bayesian statistics",
abstract = "Hardware performance counters (HPCs) that measure low-level architectural and microarchitectural events provide dynamic contextual information about the state of the system. However, HPC measurements are error-prone due to non determinism (e.g., undercounting due to event multiplexing, or OS interrupt-handling behaviors). In this paper, we present BayesPerf, a system for quantifying uncertainty in HPC measurements by using a domain-driven Bayesian model that captures microarchitectural relationships between HPCs to jointly infer their values as probability distributions. We provide the design and implementation of an accelerator that allows for low-latency and low-power inference of the BayesPerf model for x86 and ppc64 CPUs. BayesPerf reduces the average error in HPC measurements from 40.1% to 7.6% when events are being multiplexed. The value of BayesPerf in real-time decision-making is illustrated with a simple example of scheduling of PCIe transfers.",
keywords = "Accelerator, Error Correction, Error Detection, Performance Counter, Probabilistic Graphical Model, Sampling Errors",
author = "Banerjee, {Subho S.} and Saurabh Jha and Zbigniew Kalbarczyk and Iyer, {Ravishankar K.}",
note = "Funding Information: We thank the ASPLOS reviewers and our shepherd, Alexandre Passos, for their valuable comments that improved the paper. We appreciate S. Lumetta, W-M. Hwu, J. Xiong, and J. Applequist for their insightful discussion and comments on the early drafts of this manuscript. This work is partially supported by the National Science Foundation (NSF) under grant Nos. CNS 13-37732, CNS 16-24790, and CCF 20-29049; by the IBM-ILLINOIS Center for Cognitive Computing Systems Research (C3SR), a research collaboration that is part of the IBM AI Horizon Network; and by IBM, Intel, and Xilinx through equipment donations. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the Funding Information: NSF, IBM, Intel, or, Xilinx. Saurabh Jha is supported by a 2020 IBM PhD fellowship. Publisher Copyright: {\textcopyright} 2021 ACM.; 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2021 ; Conference date: 19-04-2021 Through 23-04-2021",
year = "2021",
month = apr,
day = "19",
doi = "10.1145/3445814.3446739",
language = "English (US)",
series = "International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS",
publisher = "Association for Computing Machinery",
pages = "832--844",
booktitle = "Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2021",
address = "United States",
}