@inproceedings{2e26af3ddf81418da50e90f353843f72,
title = "Balanced Distributed Memory Parallel Computers",
abstract = "Mismatches between on-chip high performance CPU and data access times is the basic reason for the increasing gap between peak and sustained performance in distributed memory parallel computers. We propose the concept of balanced architectures, based on a network with a dynamic topology and communication patterns determined at compile time. The corresponding processing element is a cacheless CPU, which can achieve a 1 FLOP/clock cycle rate. Network and PE features are presented. An example shows that balanced architectures keep efficiency when scaling.",
author = "F. Cappello and Bechennec, {J. L.} and F. Delaplace and C. Germain and Giavitto, {J. L.} and V. Neri and D. Etiemble",
note = "Funding Information: This work is partially supported by the french national research program on New Computer Architectures (PRC-ANM) and by DRET under grant #91.168. Publisher Copyright: {\textcopyright} 1993 IEEE.; 1993 International Conference on Parallel Processing, ICPP 1993 ; Conference date: 16-08-1993 Through 20-08-1993",
year = "1993",
doi = "10.1109/ICPP.1993.52",
language = "English (US)",
series = "Proceedings of the International Conference on Parallel Processing",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "72--76",
booktitle = "Architecture",
address = "United States",
}