Balanced Distributed Memory Parallel Computers

F. Cappello, J. L. Bechennec, F. Delaplace, C. Germain, J. L. Giavitto, V. Neri, D. Etiemble

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Mismatches between on-chip high performance CPU and data access times is the basic reason for the increasing gap between peak and sustained performance in distributed memory parallel computers. We propose the concept of balanced architectures, based on a network with a dynamic topology and communication patterns determined at compile time. The corresponding processing element is a cacheless CPU, which can achieve a 1 FLOP/clock cycle rate. Network and PE features are presented. An example shows that balanced architectures keep efficiency when scaling.

Original languageEnglish (US)
Title of host publicationArchitecture
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages5
ISBN (Electronic)0849389836
StatePublished - 1993
Externally publishedYes
Event1993 International Conference on Parallel Processing, ICPP 1993 - Syracuse, United States
Duration: Aug 16 1993Aug 20 1993

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918


Conference1993 International Conference on Parallel Processing, ICPP 1993
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Software
  • General Mathematics
  • Hardware and Architecture


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