Back-gated buried oxide MOSFET's in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

R. Bashir; F. Wang; W. Greig; J. M. McGregor; W. Yindeepol; J. De Santis

doi:10.1109/55.704400

Back-gated buried oxide MOSFET's in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

R. Bashir, F. Wang, W. Greig, J. M. McGregor, W. Yindeepol, J. De Santis

Research output: Contribution to journal › Article › peer-review

Abstract

A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2 × 10¹²#/cm² at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4 × 10¹⁰#/cm² in the buried oxide.

Original language	English (US)
Pages (from-to)	282-284
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	19
Issue number	8
DOIs	https://doi.org/10.1109/55.704400
State	Published - Aug 1998
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/55.704400

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title = "Back-gated buried oxide MOSFET's in a high-voltage bipolar technology for bonded oxide/SOI interface characterization",

abstract = "A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2 × 1012#/cm2 at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4 × 1010#/cm2 in the buried oxide.",

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AU - Bashir, R.

AU - Wang, F.

AU - Greig, W.

AU - McGregor, J. M.

AU - Yindeepol, W.

AU - De Santis, J.

PY - 1998/8

Y1 - 1998/8

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AB - A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2 × 1012#/cm2 at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4 × 1010#/cm2 in the buried oxide.

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Back-gated buried oxide MOSFET's in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

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