Back-gated buried oxide MOSFET's in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

Rashid Bashir, F. Wang, W. Greig, J. M. McGregor, W. Yindeepol, J. De Santis

Research output: Contribution to journalArticle

Abstract

A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2 × 1012#/cm2 at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4 × 1010#/cm2 in the buried oxide.

Original languageEnglish (US)
Pages (from-to)282-284
Number of pages3
JournalIEEE Electron Device Letters
Volume19
Issue number8
DOIs
StatePublished - Aug 1 1998
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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