AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors

Abhishek Sinkard, Nam Sung Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Power-gating devices incur a small amount of voltage drop across them when they are on in active mode, degrading the maximum frequency of processors. Thus, large power-gating devices are often implemented to minimize the drop (thus the frequency degradation), requiring considerable die area. Meanwhile, adaptive voltage scaling has been used to improve yield of power-constrained processors exhibiting a large spread of maximum frequency and total power due to process variations. In this paper, first, we analyze the impact of power-gating device size on both maximum frequency and total power of processors in the presence of process variation. Second, we propose a methodology that optimizes both the size of power-gating devices and the degree of adaptive voltage scaling jointly such that we minimize the device size while maximizing performance and power efficiency of power-constrained processors. Finally, we extend our analysis and optimization for multi-core processors adopting frequency-island clocking scheme. Our experimental results using a 32nm technology model demonstrates that the joint optimization considering both die-to-die and within-die variations reduces the size of power-gating devices by more than 50% with 3% frequency improvement for power-constrained multi-core processors. Further, the optimal size of power-gating devices for multi-core processors using the frequency-island clocking scheme increases gradually while the optimal supply voltage decreases as the number of cores per die increases.

Original languageEnglish (US)
Title of host publication2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
Pages725-730
Number of pages6
DOIs
StatePublished - Mar 28 2011
Event2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama, Japan
Duration: Jan 25 2011Jan 28 2011

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
CountryJapan
CityYokohama
Period1/25/111/28/11

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Sinkard, A., & Kim, N. S. (2011). AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors. In 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 (pp. 725-730). [5722282] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2011.5722282