Automatic Generation of Warp-Level Primitives and Atomic Instructions for Fast and Portable Parallel Reduction on GPUs

Simon Garcia De Gonzalo, Sitao Huang, Juan Gomez-Luna, Simon Hammond, Onur Mutlu, Wen Mei Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Since the advent of GPU computing, GPU hardware has evolved at a fast pace. Since application performance heavily depends on the latest hardware improvements, performance portability is extremely challenging for GPU application library developers. Portability becomes even more difficult when new low-level instructions are added to the ISA (e.g., warp shuffle instructions) or the microarchitectural support for existing instructions is improved (e.g., atomic instructions). Library developers, besides re-tuning the code for new hardware features, deal with the performance portability issue by hand-writing multiple algorithm versions that leverage different instruction sets and microarchitectures. High-level programming frameworks and Domain Specific Languages (DSLs) do not typically support low-level instructions (e.g., warp shuffle and atomic instructions), so it is painful or even impossible for these programming systems to take advantage of the latest architectural improvements. In this work, we design a new set of high-level APIs and qualifiers, as well as specialized Abstract Syntax Tree (AST) transformations for high-level programming languages and DSLs. Our transformations enable warp shuffle instructions and atomic instructions (on global and shared memories) to be easily generated. We show a practical implementation of these transformations by building on Tangram, a high-level kernel synthesis framework. Using our new language and compiler extensions, we implement parallel reduction, a fundamental building block used in a wide range of algorithms. Parallel reduction is representative of the performance portability challenge, as its performance heavily depends on the latest hardware improvements. We compare our synthesized parallel reduction to another high-level programming framework and a hand-written high-performance library across three generations of GPU architectures, and show up to 7. 8 \times speedup (2 \times on average) over hand-written code.

Original languageEnglish (US)
Title of host publicationCGO 2019 - Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization
EditorsTipp Moseley, Alexandra Jimborean, Mahmut Taylan Kandemir
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages73-84
Number of pages12
ISBN (Electronic)9781728114361
DOIs
StatePublished - Mar 5 2019
Event17th IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2019 - Washington, United States
Duration: Feb 16 2019Feb 20 2019

Publication series

NameCGO 2019 - Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization

Conference

Conference17th IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2019
CountryUnited States
CityWashington
Period2/16/192/20/19

ASJC Scopus subject areas

  • Software
  • Control and Optimization

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    Gonzalo, S. G. D., Huang, S., Gomez-Luna, J., Hammond, S., Mutlu, O., & Hwu, W. M. (2019). Automatic Generation of Warp-Level Primitives and Atomic Instructions for Fast and Portable Parallel Reduction on GPUs. In T. Moseley, A. Jimborean, & M. T. Kandemir (Eds.), CGO 2019 - Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization (pp. 73-84). [8661187] (CGO 2019 - Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CGO.2019.8661187