Automatic generation of system level assertions from transaction level models

Lingyi Liu, Shobha Vasudevan

Research output: Contribution to journalArticle


We automatically generate assertions from Transaction Level Model (TLM) simulation traces. The generated assertions express design specifications in the form of linear temporal logic with quantitative temporal constraints [4]. We first generate the assertions without regard to the quantitative time constraints. They are mined in the form of frequent patterns in the simulation traces. We mine simulation traces using episode mining to identify frequent episodes comprising function calls and events. We then annotate the episodes with real time parameters to express quantitative time constraints among the function calls or events in the episode. When mining such TLM assertions, we employ symbolic execution to generalize the parameters and return values of function calls in the traces to help the mining engine generate high quality assertions. We have constructed a realistic AXI-based interconnection network platform that we demonstrate experimental results on. We show that our technique efficiently generates high quality performance and functional assertions on the AXI-based platform as well as a transaction level AMBA-based DMA controller. We demonstrate that episode mining is more scalable and able to generate a more compact set of high quality TLM assertions than previous efforts using sequential pattern mining. The number of generated assertions using episode mining can be reduced by up to 228 times, and the time interval between two events/function calls in each assertion is smaller than 50 time units.

Original languageEnglish (US)
Pages (from-to)669-684
Number of pages16
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Issue number5
StatePublished - Oct 1 2013



  • Assertion generation
  • Episode mining
  • Symbolic execution
  • Transaction level models

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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