Automatic generation of assertions from system level design using data mining

Lingyi Liu, David Sheridan, Viraj Athavale, Shobha Vasudevan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

System level modeling is widely employed at early stages of system development for simplifying design verification and architectural exploration. Assertion based verification has become a well established part of RTL verification methodology. In the traditional assertion based verification flow, assertions are manually written. In this paper, we generate assertions from system level designs using GoldMine, an automatic assertion generation engine that uses data mining and static analysis. Candidate assertions are mined in the form of frequent patterns in the simulation traces of the system level designs. We consider both cycle accurate and transaction level designs and develop a methodology for the mining of each. For cycle accurate designs, we use both a decision tree based supervised learning algorithms as well as a coverage guided association mining algorithm to search for correlations in the simulation trace. For transaction level designs, sequential pattern mining is applied to generate frequent sequences of function calls and events from traces. We also use a symbolic execution engine to generalize the parameters and return values of the functions to help the data miner find relevant behavior. We show that our technique generates meaningful assertions on both a cycle accurate RISC CPU design and a transaction level AMBA-based DMA controller.

Original languageEnglish (US)
Title of host publication9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011
Pages191-200
Number of pages10
DOIs
StatePublished - Sep 1 2011
Event9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011 - Cambridge, United Kingdom
Duration: Jul 11 2011Jul 13 2011

Publication series

Name9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011

Other

Other9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011
CountryUnited Kingdom
CityCambridge
Period7/11/117/13/11

Fingerprint

Assertion
Data mining
Data Mining
Transactions
Mining
Trace
Cycle
Engine
Engines
Symbolic Execution
Sequential Patterns
Reduced instruction set computing
Frequent Pattern
Methodology
Miners
Supervised learning
Static analysis
Supervised Learning
Dynamic mechanical analysis
Static Analysis

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Modeling and Simulation

Cite this

Liu, L., Sheridan, D., Athavale, V., & Vasudevan, S. (2011). Automatic generation of assertions from system level design using data mining. In 9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011 (pp. 191-200). [5970526] (9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011). https://doi.org/10.1109/MEMCOD.2011.5970526

Automatic generation of assertions from system level design using data mining. / Liu, Lingyi; Sheridan, David; Athavale, Viraj; Vasudevan, Shobha.

9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011. 2011. p. 191-200 5970526 (9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liu, L, Sheridan, D, Athavale, V & Vasudevan, S 2011, Automatic generation of assertions from system level design using data mining. in 9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011., 5970526, 9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011, pp. 191-200, 9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011, Cambridge, United Kingdom, 7/11/11. https://doi.org/10.1109/MEMCOD.2011.5970526
Liu L, Sheridan D, Athavale V, Vasudevan S. Automatic generation of assertions from system level design using data mining. In 9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011. 2011. p. 191-200. 5970526. (9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011). https://doi.org/10.1109/MEMCOD.2011.5970526
Liu, Lingyi ; Sheridan, David ; Athavale, Viraj ; Vasudevan, Shobha. / Automatic generation of assertions from system level design using data mining. 9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011. 2011. pp. 191-200 (9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011).
@inproceedings{d2a0193e748a4cf08e2e331f8835ffe4,
title = "Automatic generation of assertions from system level design using data mining",
abstract = "System level modeling is widely employed at early stages of system development for simplifying design verification and architectural exploration. Assertion based verification has become a well established part of RTL verification methodology. In the traditional assertion based verification flow, assertions are manually written. In this paper, we generate assertions from system level designs using GoldMine, an automatic assertion generation engine that uses data mining and static analysis. Candidate assertions are mined in the form of frequent patterns in the simulation traces of the system level designs. We consider both cycle accurate and transaction level designs and develop a methodology for the mining of each. For cycle accurate designs, we use both a decision tree based supervised learning algorithms as well as a coverage guided association mining algorithm to search for correlations in the simulation trace. For transaction level designs, sequential pattern mining is applied to generate frequent sequences of function calls and events from traces. We also use a symbolic execution engine to generalize the parameters and return values of the functions to help the data miner find relevant behavior. We show that our technique generates meaningful assertions on both a cycle accurate RISC CPU design and a transaction level AMBA-based DMA controller.",
author = "Lingyi Liu and David Sheridan and Viraj Athavale and Shobha Vasudevan",
year = "2011",
month = "9",
day = "1",
doi = "10.1109/MEMCOD.2011.5970526",
language = "English (US)",
isbn = "9781457701160",
series = "9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011",
pages = "191--200",
booktitle = "9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011",

}

TY - GEN

T1 - Automatic generation of assertions from system level design using data mining

AU - Liu, Lingyi

AU - Sheridan, David

AU - Athavale, Viraj

AU - Vasudevan, Shobha

PY - 2011/9/1

Y1 - 2011/9/1

N2 - System level modeling is widely employed at early stages of system development for simplifying design verification and architectural exploration. Assertion based verification has become a well established part of RTL verification methodology. In the traditional assertion based verification flow, assertions are manually written. In this paper, we generate assertions from system level designs using GoldMine, an automatic assertion generation engine that uses data mining and static analysis. Candidate assertions are mined in the form of frequent patterns in the simulation traces of the system level designs. We consider both cycle accurate and transaction level designs and develop a methodology for the mining of each. For cycle accurate designs, we use both a decision tree based supervised learning algorithms as well as a coverage guided association mining algorithm to search for correlations in the simulation trace. For transaction level designs, sequential pattern mining is applied to generate frequent sequences of function calls and events from traces. We also use a symbolic execution engine to generalize the parameters and return values of the functions to help the data miner find relevant behavior. We show that our technique generates meaningful assertions on both a cycle accurate RISC CPU design and a transaction level AMBA-based DMA controller.

AB - System level modeling is widely employed at early stages of system development for simplifying design verification and architectural exploration. Assertion based verification has become a well established part of RTL verification methodology. In the traditional assertion based verification flow, assertions are manually written. In this paper, we generate assertions from system level designs using GoldMine, an automatic assertion generation engine that uses data mining and static analysis. Candidate assertions are mined in the form of frequent patterns in the simulation traces of the system level designs. We consider both cycle accurate and transaction level designs and develop a methodology for the mining of each. For cycle accurate designs, we use both a decision tree based supervised learning algorithms as well as a coverage guided association mining algorithm to search for correlations in the simulation trace. For transaction level designs, sequential pattern mining is applied to generate frequent sequences of function calls and events from traces. We also use a symbolic execution engine to generalize the parameters and return values of the functions to help the data miner find relevant behavior. We show that our technique generates meaningful assertions on both a cycle accurate RISC CPU design and a transaction level AMBA-based DMA controller.

UR - http://www.scopus.com/inward/record.url?scp=80052121452&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052121452&partnerID=8YFLogxK

U2 - 10.1109/MEMCOD.2011.5970526

DO - 10.1109/MEMCOD.2011.5970526

M3 - Conference contribution

SN - 9781457701160

T3 - 9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011

SP - 191

EP - 200

BT - 9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011

ER -