@inproceedings{d4993fa30e084fdab57ecb438951ce20,
title = "Automatic bus planner for dense PCBs",
abstract = "Since no commercial PCB routing tools can solve the routing problem for today's complex PCBs, these circuit boards have to be routed manually, taking about 2 months of time per board. Bus planning is one of the most time-consuming steps of PCB routing. It consists of assigning buses to multiple layers of the PCB and routing them in a planar fashion on each layer. Routing congestion between on-board components and the min-max length bounds of the buses must also be considered during routing. In this paper, we present the first automatic bus planner. We tested our system on a state-of-the-art industrial circuit board with over 7000 nets and 12 signal layers. All the nets on this board were already manually routed. Our bus planner is able to achieve 100% routing completion using the layer assignment extracted from manual design. For simultaneous layer assignment and bus routing, we are able to successfully route 98.5% of the nets. The remaining 1.5% can be routed either manually or by using vias. The runtime of our bus planner is less than 3 hours on a 3 Ghz workstation.",
keywords = "Bus planning, Layer assignment, PCB routing, Topological routing",
author = "Kong Hui and Yan Tan and Wong, {Martin D.F.}",
note = "Funding Information: This work has been supported in part by CNR, Progetto Finalizzato Chimica Fine.; 2009 46th ACM/IEEE Design Automation Conference, DAC 2009 ; Conference date: 26-07-2009 Through 31-07-2009",
year = "2009",
doi = "10.1145/1629911.1630000",
language = "English (US)",
isbn = "9781605584973",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "326--331",
booktitle = "2009 46th ACM/IEEE Design Automation Conference, DAC 2009",
address = "United States",
}