Automated mapping of pre-computed module-level test sequences to processor instructions

Keyphrases

• Test Sequence 100%
• Module Level 100%
• Automatic Mapping 100%
• Processor Instructions 100%
• Temporal Logic Properties 33%
• Novel Technique 16%
• Test Case Generation 16%
• Test Validity 16%
• Design Phase 16%
• Caching 16%
• Model Checker 16%
• Instruction Sequences 16%
• Defect Coverage 16%
• Undetected Faults 16%
• Bounded Model Checker 16%

Computer Science

• Temporal Logic 100%
• model checker 100%
• Processor Instruction 100%
• Test Generation 50%
• Design Phase 50%
• Instruction Sequence 50%