Automated mapping of pre-computed module-level test sequences to processor instructions

Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Executing instructions from the cache has been shown to improve the defect coverage of real chips. However, although the faults detected by such tests can be deteremined, there has been no technique to target test generation for an undetected fault. This paper presents a novel technique to map pre-computed test sequences at the module level of a processor, to sequences of instructions. The module level pre-computed test sequence is translated into a temporal logic property and the negation of the property is passed to a bounded model checker. The model checker produces a counter-example for the temporal logic property. This counter-example trace contains the instruction sequence that can be applied at the primary inputs to produce the pre-computed test sequence at the module inputs. This technique has no restrictions on the type of test sequences, so it can be used to map test sequences for any kind of fault to processor instructions. It can also be used in the design phase to produce validation tests.

Original languageEnglish (US)
Title of host publicationIEEE International Test Conference, Proceedings, ITC 2005
Number of pages10
StatePublished - 2005
Externally publishedYes
EventIEEE International Test Conference, ITC 2005 - Austin, TX, United States
Duration: Nov 8 2005Nov 10 2005

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


OtherIEEE International Test Conference, ITC 2005
Country/TerritoryUnited States
CityAustin, TX

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics


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