Automated mapping of pre-computed module-level test sequences to processor instructions

Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Executing instructions from the cache has been shown to improve the defect coverage of real chips. However, although the faults detected by such tests can be deteremined, there has been no technique to target test generation for an undetected fault. This paper presents a novel technique to map pre-computed test sequences at the module level of a processor, to sequences of instructions. The module level pre-computed test sequence is translated into a temporal logic property and the negation of the property is passed to a bounded model checker. The model checker produces a counter-example for the temporal logic property. This counter-example trace contains the instruction sequence that can be applied at the primary inputs to produce the pre-computed test sequence at the module inputs. This technique has no restrictions on the type of test sequences, so it can be used to map test sequences for any kind of fault to processor instructions. It can also be used in the design phase to produce validation tests.

Original languageEnglish (US)
Title of host publicationIEEE International Test Conference, Proceedings, ITC 2005
Pages294-303
Number of pages10
DOIs
StatePublished - Dec 1 2005
EventIEEE International Test Conference, ITC 2005 - Austin, TX, United States
Duration: Nov 8 2005Nov 10 2005

Publication series

NameProceedings - International Test Conference
Volume2005
ISSN (Print)1089-3539

Other

OtherIEEE International Test Conference, ITC 2005
CountryUnited States
CityAustin, TX
Period11/8/0511/10/05

Fingerprint

Temporal logic
Module
Fault
Defects
Temporal Logic
Counterexample
Test Generation
Cache
Coverage
Chip
Trace
Restriction
Target
Model

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Gurumurthy, S., Vasudevan, S., & Abraham, J. A. (2005). Automated mapping of pre-computed module-level test sequences to processor instructions. In IEEE International Test Conference, Proceedings, ITC 2005 (pp. 294-303). [1583987] (Proceedings - International Test Conference; Vol. 2005). https://doi.org/10.1109/TEST.2005.1583987

Automated mapping of pre-computed module-level test sequences to processor instructions. / Gurumurthy, Sankar; Vasudevan, Shobha; Abraham, Jacob A.

IEEE International Test Conference, Proceedings, ITC 2005. 2005. p. 294-303 1583987 (Proceedings - International Test Conference; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gurumurthy, S, Vasudevan, S & Abraham, JA 2005, Automated mapping of pre-computed module-level test sequences to processor instructions. in IEEE International Test Conference, Proceedings, ITC 2005., 1583987, Proceedings - International Test Conference, vol. 2005, pp. 294-303, IEEE International Test Conference, ITC 2005, Austin, TX, United States, 11/8/05. https://doi.org/10.1109/TEST.2005.1583987
Gurumurthy S, Vasudevan S, Abraham JA. Automated mapping of pre-computed module-level test sequences to processor instructions. In IEEE International Test Conference, Proceedings, ITC 2005. 2005. p. 294-303. 1583987. (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2005.1583987
Gurumurthy, Sankar ; Vasudevan, Shobha ; Abraham, Jacob A. / Automated mapping of pre-computed module-level test sequences to processor instructions. IEEE International Test Conference, Proceedings, ITC 2005. 2005. pp. 294-303 (Proceedings - International Test Conference).
@inproceedings{ce2bb44844d040369262513858ae770e,
title = "Automated mapping of pre-computed module-level test sequences to processor instructions",
abstract = "Executing instructions from the cache has been shown to improve the defect coverage of real chips. However, although the faults detected by such tests can be deteremined, there has been no technique to target test generation for an undetected fault. This paper presents a novel technique to map pre-computed test sequences at the module level of a processor, to sequences of instructions. The module level pre-computed test sequence is translated into a temporal logic property and the negation of the property is passed to a bounded model checker. The model checker produces a counter-example for the temporal logic property. This counter-example trace contains the instruction sequence that can be applied at the primary inputs to produce the pre-computed test sequence at the module inputs. This technique has no restrictions on the type of test sequences, so it can be used to map test sequences for any kind of fault to processor instructions. It can also be used in the design phase to produce validation tests.",
author = "Sankar Gurumurthy and Shobha Vasudevan and Abraham, {Jacob A.}",
year = "2005",
month = "12",
day = "1",
doi = "10.1109/TEST.2005.1583987",
language = "English (US)",
isbn = "0780390393",
series = "Proceedings - International Test Conference",
pages = "294--303",
booktitle = "IEEE International Test Conference, Proceedings, ITC 2005",

}

TY - GEN

T1 - Automated mapping of pre-computed module-level test sequences to processor instructions

AU - Gurumurthy, Sankar

AU - Vasudevan, Shobha

AU - Abraham, Jacob A.

PY - 2005/12/1

Y1 - 2005/12/1

N2 - Executing instructions from the cache has been shown to improve the defect coverage of real chips. However, although the faults detected by such tests can be deteremined, there has been no technique to target test generation for an undetected fault. This paper presents a novel technique to map pre-computed test sequences at the module level of a processor, to sequences of instructions. The module level pre-computed test sequence is translated into a temporal logic property and the negation of the property is passed to a bounded model checker. The model checker produces a counter-example for the temporal logic property. This counter-example trace contains the instruction sequence that can be applied at the primary inputs to produce the pre-computed test sequence at the module inputs. This technique has no restrictions on the type of test sequences, so it can be used to map test sequences for any kind of fault to processor instructions. It can also be used in the design phase to produce validation tests.

AB - Executing instructions from the cache has been shown to improve the defect coverage of real chips. However, although the faults detected by such tests can be deteremined, there has been no technique to target test generation for an undetected fault. This paper presents a novel technique to map pre-computed test sequences at the module level of a processor, to sequences of instructions. The module level pre-computed test sequence is translated into a temporal logic property and the negation of the property is passed to a bounded model checker. The model checker produces a counter-example for the temporal logic property. This counter-example trace contains the instruction sequence that can be applied at the primary inputs to produce the pre-computed test sequence at the module inputs. This technique has no restrictions on the type of test sequences, so it can be used to map test sequences for any kind of fault to processor instructions. It can also be used in the design phase to produce validation tests.

UR - http://www.scopus.com/inward/record.url?scp=33847103496&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847103496&partnerID=8YFLogxK

U2 - 10.1109/TEST.2005.1583987

DO - 10.1109/TEST.2005.1583987

M3 - Conference contribution

SN - 0780390393

SN - 9780780390393

T3 - Proceedings - International Test Conference

SP - 294

EP - 303

BT - IEEE International Test Conference, Proceedings, ITC 2005

ER -