Automated Communication and Floorplan-Aware Hardware/Software Co-Design for SoC

Jong Bin Lim, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The main objective of modern SoC (System-on-Chip) designs is to achieve high-performance while maintaining low power consumption and resource usage. However, achieving such a goal is a difficult and time-consuming engineering task due to the vast design space of hardware accelerators and HW/SW task partitioning. Depending on the partitioning decision, communication between parts of the SoC must be also optimized such that the overall runtime including both computation and communication would be fast. In this paper, we propose an automated approach to iteratively search for a near-optimal SoC design with minimum latency within the targeted power and resource budget. Our approach consists of the following main components: (1) polyhedral-model-based hardware accelerator design space exploration, (2) modeling of various communication types and integration into LLVM-based integer linear programming for HW/SW task partitioning, (3) fast and efficient search algorithm to extract maximum operating frequency using floorplanner, and (4) back-annotation of extracted information to system level for iterative partitioning. Using FPGA as the target platform, we demonstrate that our approach consistently outperforms the previous state-of-the-art solutions for automated HW/SW co-design by 37.8% on average and up to 75.2% for certain designs.

Original languageEnglish (US)
Title of host publicationProceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
PublisherIEEE Computer Society
Pages128-133
Number of pages6
ISBN (Electronic)9781538670996
DOIs
StatePublished - Jul 2019
Event18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 - Miami, United States
Duration: Jul 15 2019Jul 17 2019

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2019-July
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Conference

Conference18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
CountryUnited States
CityMiami
Period7/15/197/17/19

Keywords

  • Floorplanning
  • HW/SW Partitioning
  • Near-Optimal
  • System-on-Chip (SoC)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Automated Communication and Floorplan-Aware Hardware/Software Co-Design for SoC'. Together they form a unique fingerprint.

  • Cite this

    Lim, J. B., & Chen, D. (2019). Automated Communication and Floorplan-Aware Hardware/Software Co-Design for SoC. In Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 (pp. 128-133). [8839408] (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2019.00032