TY - GEN
T1 - Automated Communication and Floorplan-Aware Hardware/Software Co-Design for SoC
AU - Lim, Jong Bin
AU - Chen, Deming
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - The main objective of modern SoC (System-on-Chip) designs is to achieve high-performance while maintaining low power consumption and resource usage. However, achieving such a goal is a difficult and time-consuming engineering task due to the vast design space of hardware accelerators and HW/SW task partitioning. Depending on the partitioning decision, communication between parts of the SoC must be also optimized such that the overall runtime including both computation and communication would be fast. In this paper, we propose an automated approach to iteratively search for a near-optimal SoC design with minimum latency within the targeted power and resource budget. Our approach consists of the following main components: (1) polyhedral-model-based hardware accelerator design space exploration, (2) modeling of various communication types and integration into LLVM-based integer linear programming for HW/SW task partitioning, (3) fast and efficient search algorithm to extract maximum operating frequency using floorplanner, and (4) back-annotation of extracted information to system level for iterative partitioning. Using FPGA as the target platform, we demonstrate that our approach consistently outperforms the previous state-of-the-art solutions for automated HW/SW co-design by 37.8% on average and up to 75.2% for certain designs.
AB - The main objective of modern SoC (System-on-Chip) designs is to achieve high-performance while maintaining low power consumption and resource usage. However, achieving such a goal is a difficult and time-consuming engineering task due to the vast design space of hardware accelerators and HW/SW task partitioning. Depending on the partitioning decision, communication between parts of the SoC must be also optimized such that the overall runtime including both computation and communication would be fast. In this paper, we propose an automated approach to iteratively search for a near-optimal SoC design with minimum latency within the targeted power and resource budget. Our approach consists of the following main components: (1) polyhedral-model-based hardware accelerator design space exploration, (2) modeling of various communication types and integration into LLVM-based integer linear programming for HW/SW task partitioning, (3) fast and efficient search algorithm to extract maximum operating frequency using floorplanner, and (4) back-annotation of extracted information to system level for iterative partitioning. Using FPGA as the target platform, we demonstrate that our approach consistently outperforms the previous state-of-the-art solutions for automated HW/SW co-design by 37.8% on average and up to 75.2% for certain designs.
KW - Floorplanning
KW - HW/SW Partitioning
KW - Near-Optimal
KW - System-on-Chip (SoC)
UR - http://www.scopus.com/inward/record.url?scp=85072970615&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85072970615&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2019.00032
DO - 10.1109/ISVLSI.2019.00032
M3 - Conference contribution
AN - SCOPUS:85072970615
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 128
EP - 133
BT - Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
PB - IEEE Computer Society
T2 - 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Y2 - 15 July 2019 through 17 July 2019
ER -