Asynchronous comparison-based decoders for delay-insensitive codes

Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo

Research output: Contribution to journalReview articlepeer-review

Abstract

A comparison-based decoder detects the arrival of a code word by comparing the received checkbits with the checkbits computed using the received data. Implementation issues underlying comparison-based decoders for systematic delay-insensitive (DI) or unordered codes is the subject of this paper. We show that if the decoder is to be implemented using asynchronous logic, i.e., if the gate and wire delays are arbitrary (unbounded but finite), then it is impossible to design a comparison-based decoder for any code that is more efficient than a dual-rail code. In other words, the encoded word must contain at least twice as many bits as the data. In addition, the codes should satisfy two other properties, called the initial condition and the all-zero lower triangle (AZLT) property, for the realization of a delay-insensitive comparison-based decoder. The paper shows that comparison-based decoders for codes that have the requisite level of redundancy and that satisfy the two properties can be implemented using asynchronous logic.

Original languageEnglish (US)
Pages (from-to)802-811
Number of pages10
JournalIEEE Transactions on Computers
Volume47
Issue number7
DOIs
StatePublished - 1998

Keywords

  • Block codes
  • Delay-insensitive codes
  • Delay-insensitive communication
  • Self-timed design

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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