TY - GEN
T1 - A2M
T2 - 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019
AU - Wang, Dong Kai
AU - Sung Kim, Nam
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - Emerging applications today operate on increasingly larger data sets, and as a result, the memory subsystem is prone to be a bottleneck in bandwidth and capacity. Many of these applications store data based on real world phenomena which often have continuity properties and can be approximated by mathematical functions. In this work, we view computer memory abstractly as a set of functions that map each address input to a data output. We propose Approximate Algebraic Memory (A2M), a specialized memory model that uses finite degree polynomials to approximate ranges of memory content with the desired properties. Specifically, A2M uses dedicated hardware to derive and store polynomial coefficients rather than memory data. In error resilient workloads, the benefits of this design is threefold: (1) high ratio memory compression, (2) high bandwidth accesses, and (3) direct computation on memory. We evaluate A2M's potential as an on-chip structure for general-purpose processors, and as a specialized read-only memory for neural network accelerators. Our results show that for CPU workloads, A2M yields minimal error (< 1%) at a fixed compression ratio of 16, and improves performance by 11.3% on average.
AB - Emerging applications today operate on increasingly larger data sets, and as a result, the memory subsystem is prone to be a bottleneck in bandwidth and capacity. Many of these applications store data based on real world phenomena which often have continuity properties and can be approximated by mathematical functions. In this work, we view computer memory abstractly as a set of functions that map each address input to a data output. We propose Approximate Algebraic Memory (A2M), a specialized memory model that uses finite degree polynomials to approximate ranges of memory content with the desired properties. Specifically, A2M uses dedicated hardware to derive and store polynomial coefficients rather than memory data. In error resilient workloads, the benefits of this design is threefold: (1) high ratio memory compression, (2) high bandwidth accesses, and (3) direct computation on memory. We evaluate A2M's potential as an on-chip structure for general-purpose processors, and as a specialized read-only memory for neural network accelerators. Our results show that for CPU workloads, A2M yields minimal error (< 1%) at a fixed compression ratio of 16, and improves performance by 11.3% on average.
KW - Approximate Computing
KW - Data Compression
KW - Memory Architecture
UR - http://www.scopus.com/inward/record.url?scp=85072672571&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85072672571&partnerID=8YFLogxK
U2 - 10.1109/ISLPED.2019.8824846
DO - 10.1109/ISLPED.2019.8824846
M3 - Conference contribution
AN - SCOPUS:85072672571
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
BT - International Symposium on Low Power Electronics and Design, ISLPED 2019
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 29 July 2019 through 31 July 2019
ER -