ARRAY OPTIMIZATION FOR VLSI SYNTHESIS.

Martin D F Wong, C. L. Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An algorithm that solves a general array-optimization problem is presented. The algorithm can be used for compacting gate matrix layouts, SLAs, Weinberger arrays, and for multiple folding of PLAs. The approach is based on the technique of simulated annealing. The solution space is formulated such that it facilitates an effective search for an optimal solution. Experimental results are very encouraging.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherIEEE
Pages537-543
Number of pages7
ISBN (Print)0818607815
StatePublished - Jan 1 1987

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123

Fingerprint

Simulated annealing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Wong, M. D. F., & Liu, C. L. (1987). ARRAY OPTIMIZATION FOR VLSI SYNTHESIS. In Proceedings - Design Automation Conference (pp. 537-543). (Proceedings - Design Automation Conference). IEEE.

ARRAY OPTIMIZATION FOR VLSI SYNTHESIS. / Wong, Martin D F; Liu, C. L.

Proceedings - Design Automation Conference. IEEE, 1987. p. 537-543 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wong, MDF & Liu, CL 1987, ARRAY OPTIMIZATION FOR VLSI SYNTHESIS. in Proceedings - Design Automation Conference. Proceedings - Design Automation Conference, IEEE, pp. 537-543.
Wong MDF, Liu CL. ARRAY OPTIMIZATION FOR VLSI SYNTHESIS. In Proceedings - Design Automation Conference. IEEE. 1987. p. 537-543. (Proceedings - Design Automation Conference).
Wong, Martin D F ; Liu, C. L. / ARRAY OPTIMIZATION FOR VLSI SYNTHESIS. Proceedings - Design Automation Conference. IEEE, 1987. pp. 537-543 (Proceedings - Design Automation Conference).
@inproceedings{459f2e7211fe4ea5a7db8bce6c67b6a4,
title = "ARRAY OPTIMIZATION FOR VLSI SYNTHESIS.",
abstract = "An algorithm that solves a general array-optimization problem is presented. The algorithm can be used for compacting gate matrix layouts, SLAs, Weinberger arrays, and for multiple folding of PLAs. The approach is based on the technique of simulated annealing. The solution space is formulated such that it facilitates an effective search for an optimal solution. Experimental results are very encouraging.",
author = "Wong, {Martin D F} and Liu, {C. L.}",
year = "1987",
month = "1",
day = "1",
language = "English (US)",
isbn = "0818607815",
series = "Proceedings - Design Automation Conference",
publisher = "IEEE",
pages = "537--543",
booktitle = "Proceedings - Design Automation Conference",

}

TY - GEN

T1 - ARRAY OPTIMIZATION FOR VLSI SYNTHESIS.

AU - Wong, Martin D F

AU - Liu, C. L.

PY - 1987/1/1

Y1 - 1987/1/1

N2 - An algorithm that solves a general array-optimization problem is presented. The algorithm can be used for compacting gate matrix layouts, SLAs, Weinberger arrays, and for multiple folding of PLAs. The approach is based on the technique of simulated annealing. The solution space is formulated such that it facilitates an effective search for an optimal solution. Experimental results are very encouraging.

AB - An algorithm that solves a general array-optimization problem is presented. The algorithm can be used for compacting gate matrix layouts, SLAs, Weinberger arrays, and for multiple folding of PLAs. The approach is based on the technique of simulated annealing. The solution space is formulated such that it facilitates an effective search for an optimal solution. Experimental results are very encouraging.

UR - http://www.scopus.com/inward/record.url?scp=0023255062&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023255062&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0023255062

SN - 0818607815

T3 - Proceedings - Design Automation Conference

SP - 537

EP - 543

BT - Proceedings - Design Automation Conference

PB - IEEE

ER -