ARRAY OPTIMIZATION FOR VLSI SYNTHESIS.

D. F. Wong, C. L. Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An algorithm that solves a general array-optimization problem is presented. The algorithm can be used for compacting gate matrix layouts, SLAs, Weinberger arrays, and for multiple folding of PLAs. The approach is based on the technique of simulated annealing. The solution space is formulated such that it facilitates an effective search for an optimal solution. Experimental results are very encouraging.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherIEEE
Pages537-543
Number of pages7
ISBN (Print)0818607815, 9780818607813
DOIs
StatePublished - 1987

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Wong, D. F., & Liu, C. L. (1987). ARRAY OPTIMIZATION FOR VLSI SYNTHESIS. In Proceedings - Design Automation Conference (pp. 537-543). (Proceedings - Design Automation Conference). IEEE. https://doi.org/10.1145/37888.37968