Area optimization for general floorplans: An analogy to resistive networks

Khe Sing The, D. F. Wong

Research output: Contribution to journalConference articlepeer-review

Abstract

The authors present an algorithm for general floorplans in which each module has an infinite set of possible dimensions. Given the topology of a floorplan and the possible dimensions of the modules, the floorplan area optimization problem is to determine the dimensions of all the modules in order to minimize the floorplan area. The optimization algorithm is based on an analogy between reducing floorplan area and solving resistive network equations. Experimental results show that the algorithm outperforms the one proposed by D. F. Wong and P. Sakhamuri (1989).

Original languageEnglish (US)
Pages (from-to)2056-2059
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - Dec 1 1991
Externally publishedYes
Event1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore
Duration: Jun 11 1991Jun 14 1991

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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