Abstract
The authors present an algorithm for general floorplans in which each module has an infinite set of possible dimensions. Given the topology of a floorplan and the possible dimensions of the modules, the floorplan area optimization problem is to determine the dimensions of all the modules in order to minimize the floorplan area. The optimization algorithm is based on an analogy between reducing floorplan area and solving resistive network equations. Experimental results show that the algorithm outperforms the one proposed by D. F. Wong and P. Sakhamuri (1989).
| Original language | English (US) |
|---|---|
| Pages (from-to) | 2056-2059 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 4 |
| State | Published - Dec 1 1991 |
| Externally published | Yes |
| Event | 1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore Duration: Jun 11 1991 → Jun 14 1991 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering