Area of optimization for higher order hierarchical floorplans

Khe Sing The, D. F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The floorplan area optimization problem is to determine the dimensions of each module when the topology of the floorplan is given. The objective is to minimize the area of the resulting floorplan. We present in this paper an algorithm for general hierarchical floorplans. The shape curves for non-slicing configurations are constructed by operations on the graph representations of the floorplan. The points of a shape curve are determined by simultaneously reducing the length of all longest paths of the vertical adjacency graph, using a minimum cut technique. The algorithm is applicable to hierarchical floorplan of high order, and to modules with infinite set of possible dimensions.

Original languageEnglish (US)
Title of host publicationIEEE International Conference on Computer Design - VLSI in Computers and Processors
PublisherPubl by IEEE
Pages520-523
Number of pages4
ISBN (Print)0818622709
StatePublished - 1991
Externally publishedYes
EventProceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91 - Cambridge, MA, USA
Duration: Oct 14 1991Oct 16 1991

Publication series

NameIEEE International Conference on Computer Design - VLSI in Computers and Processors

Other

OtherProceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91
CityCambridge, MA, USA
Period10/14/9110/16/91

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

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