Area-efficient VLSI implementation of FIR digital filters using shifted partial products

Christopher Young, Douglas L Jones

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The authors describe a novel method of computing scalar-vector products based on shifted partial products of the vector elements. The method achieves a severalfold reduction in the computation required to implement a scalar-vector product. Of interest is the application of this idea to the highly parallel, area-efficient VLSI implementation of a finite impulse response digital filter in the transpose form. The reduction in computation translates into an overall decrease in chip area required for a VLSI layout of the filter. As an example in a representative VLSI technology, a pipelined design yields a 30% decrease in chip area per tap and a 20% decrease in overall chip area compared to a modified Booth's multiplier implementation.

Original languageEnglish (US)
Title of host publicationConference Record - Asilomar Conference on Circuits, Systems & Computers
PublisherPubl by Maple Press, Inc
Pages398-402
Number of pages5
Volume1
ISBN (Print)0818624701
StatePublished - 1991
Externally publishedYes
Event25th Asilomar Conference on Signals, Systems & Computers Part 1 (of 2) - Pacific Grove, CA, USA
Duration: Nov 4 1991Nov 6 1991

Other

Other25th Asilomar Conference on Signals, Systems & Computers Part 1 (of 2)
CityPacific Grove, CA, USA
Period11/4/9111/6/91

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Young, C., & Jones, D. L. (1991). Area-efficient VLSI implementation of FIR digital filters using shifted partial products. In Conference Record - Asilomar Conference on Circuits, Systems & Computers (Vol. 1, pp. 398-402). Publ by Maple Press, Inc.