Area efficient phase calibration of a 1.6 GHz multiphase DLL

Ankur Agrawal, Pavan Kumar Hanumolu, Gu Yeon Wei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL). The calibration scheme employs sub-sampling using a frequency-offset clock with respect to the DLL reference clock, to measure phase-offsets. The phase-correction circuit uses one digital-to-analog converter across eight variable-delay buffers to reduce the area consumption by 62%. The test-chip, designed in a 130nm CMOS process, demonstrates a 8-phase 1.6 GHz DLL with a worst-case phase error of 450 fs.

Original languageEnglish (US)
Title of host publication2011 IEEE Custom Integrated Circuits Conference, CICC 2011
DOIs
StatePublished - Nov 9 2011
Externally publishedYes
Event33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011 - San Jose, CA, United States
Duration: Sep 19 2011Sep 21 2011

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011
Country/TerritoryUnited States
CitySan Jose, CA
Period9/19/119/21/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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