We present an area-efficient MAP-based turbo equalizer VLSI architecture by proposing a symbol-based soft-input soft-output (SISO) kernel which processes one multi-bit symbol in every clock cycle. The symbol-based SISO hardware can be shared by the equalizer and decoder, thereby reducing silicon area. Further, by introducing block-interleaved computation in the add-compare-select recursions, the critical path delay is reduced, thereby improving throughput. Experimental results with QPSK modulation and K ⊃ 5 encoder demonstrate that the proposed area-efficient architecture achieves area savings of 47% with 11% throughput gain in a 0.25 μm CMOS process. It is also shown that the throughput is improved by 79% via block-interleaved computation with an area savings of 25%.

Original languageEnglish (US)
Title of host publication2003 IEEE Workshop on Signal Processing Systems
Subtitle of host publicationDesign and Implementation, SIPS 2003
EditorsWonyong Sung, Myung Hoon Sunwoo
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)0780377958
StatePublished - 2003
Event2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 - Seoul, Korea, Republic of
Duration: Aug 27 2003Aug 29 2003

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130


Other2003 IEEE Workshop on Signal Processing Systems, SIPS 2003
Country/TerritoryKorea, Republic of


  • Clocks
  • Computer architecture
  • Decoding
  • Delay
  • Equalizers
  • Hardware
  • Kernel
  • Silicon
  • Throughput
  • Very large scale integration

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture


Dive into the research topics of 'Area-efficient high-throughput VLSI architecture for MAP-based turbo equalizer'. Together they form a unique fingerprint.

Cite this