Area and energy-efficient crosstalk avoidance codes for on-chip buses

Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Capacitive crosstalk between adjacent wires in long on-chip buses significantly increases propagation delay in the deep submicron regime. A high-speed bus can be designed by eliminating crosstalk delay through bus encoding. In this paper, we present an overview of the existing coding schemes and show that they require either a large wiring overhead or complex encoder-decoder circuits. We propose a family of codes referred to as overlapping codes that reduce both overheads. We construct two codes from this family and demonstrate their superiority over existing schemes in terms of area and energy dissipation. Specifically, for a 1-cm 32-bit bus in 0.13-μm CMOS technology, we present a 48-wire solution that has 1.98 × speed-up, 10% energy savings and requires 20% less area than shielding.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors, ICCD 2004
Pages12-17
Number of pages6
DOIs
StatePublished - Dec 1 2004
EventProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States
Duration: Oct 11 2004Oct 13 2004

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)1063-6404

Other

OtherProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004
Country/TerritoryUnited States
CitySan Jose, CA
Period10/11/0410/13/04

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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